Patent US3887901A successfully refreshed from Google Patents.
US3887901A
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US
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Longitudinal parity generator for mainframe memories
Assignee: Unisys Corp
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Filing: 1974-04-29
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Granted: 1975-06-03
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Expires: 1994-04-29
Abstract
Abstract A network for continuously generating a longitudinal parity word for the main memory of a digital computer as new data is entered therein. The network includes a register having a number of stages equal to the word size of the memory, for storing the instantaneous value of the longitudinal word, plural Exclusive OR circuits connected individually to the input of each of the stages and having a first input of each connected to the output of the corresponding parity register stage and a second input of each Exclusive OR circuit adapted to be selectively connected alternately to the output of individual stages of either the memory write data register or its output register.
Inventors
- 👤 Iii Harry Winthrop Moore
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 18:33
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/08; G06F11/10; G06F11/1004
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
297 words
A circuit for continuously generating a longitudinal parity word each time a new item of data is entered into a computer memory device comprising in combination: a. a memory for storing digital information at addressable locations therein; b. A first multistage register connected to said memory for at least temporarily storing a data word to be entered into said memory at a predetermined address; c. a second multistage register connected to the output of said memory adapted to at least temporarily hold the data word stored in said memory at said predetermined address which is to be replaced with the data word in said first register; d. a longitudinal parity word register having a number of individual stages equal in number to the size of said data word for storing a binary number representative of the parity word which when added to the words stored in said memory will cause the total number of bits occupying a given bit position in all of said words in said memory to be odd or even; e. a plurality of Exclusive OR logic circuits equal in number to the number of bits in said data words having first and second input terminals and an output terminal, said output terminal of each of said logic circuits being connected individually to an input of a separate one of said stages of said parity word register; f. means coNnecting the output of each of said stages in said parity word register individually to the first of said input terminals of said logic circuit associated with that stage; and g. means for alternately connecting the outputs from the individual stages of said first and second registers to said second terminal of said logic circuit associated with the corresponding stage of said parity word register.
Claim 2
Dependent Claim
297 words
A circuit for continuously generating a longitudinal parity word each time a new item of data is entered into a computer memory device comprising in combination: a. a memory for storing digital information at addressable locations therein; b. A first multistage register connected to said memory for at least temporarily storing a data word to be entered into said memory at a predetermined address; c. a second multistage register connected to the output of said memory adapted to at least temporarily hold the data word stored in said memory at said predetermined address which is to be replaced with the data word in said first register; d. a longitudinal parity word register having a number of individual stages equal in number to the size of said data word for storing a binary number representative of the parity word which when added to the words stored in said memory will cause the total number of bits occupying a given bit position in all of said words in said memory to be odd or even; e. a plurality of Exclusive OR logic circuits equal in number to the number of bits in said data words having first and second input terminals and an output terminal, said output terminal of each of said logic circuits being connected individually to an input of a separate one of said stages of said parity word register; f. means coNnecting the output of each of said stages in said parity word register individually to the first of said input terminals of said logic circuit associated with that stage; and g. means for alternately connecting the outputs from the individual stages of said first and second registers to said second terminal of said logic circuit associated with the corresponding stage of said parity word register.
Claim 3
Dependent Claim
297 words
A circuit for continuously generating a longitudinal parity word each time a new item of data is entered into a computer memory device comprising in combination: a. a memory for storing digital information at addressable locations therein; b. A first multistage register connected to said memory for at least temporarily storing a data word to be entered into said memory at a predetermined address; c. a second multistage register connected to the output of said memory adapted to at least temporarily hold the data word stored in said memory at said predetermined address which is to be replaced with the data word in said first register; d. a longitudinal parity word register having a number of individual stages equal in number to the size of said data word for storing a binary number representative of the parity word which when added to the words stored in said memory will cause the total number of bits occupying a given bit position in all of said words in said memory to be odd or even; e. a plurality of Exclusive OR logic circuits equal in number to the number of bits in said data words having first and second input terminals and an output terminal, said output terminal of each of said logic circuits being connected individually to an input of a separate one of said stages of said parity word register; f. means coNnecting the output of each of said stages in said parity word register individually to the first of said input terminals of said logic circuit associated with that stage; and g. means for alternately connecting the outputs from the individual stages of said first and second registers to said second terminal of said logic circuit associated with the corresponding stage of said parity word register.
Claim 4
Dependent Claim
297 words
A circuit for continuously generating a longitudinal parity word each time a new item of data is entered into a computer memory device comprising in combination: a. a memory for storing digital information at addressable locations therein; b. A first multistage register connected to said memory for at least temporarily storing a data word to be entered into said memory at a predetermined address; c. a second multistage register connected to the output of said memory adapted to at least temporarily hold the data word stored in said memory at said predetermined address which is to be replaced with the data word in said first register; d. a longitudinal parity word register having a number of individual stages equal in number to the size of said data word for storing a binary number representative of the parity word which when added to the words stored in said memory will cause the total number of bits occupying a given bit position in all of said words in said memory to be odd or even; e. a plurality of Exclusive OR logic circuits equal in number to the number of bits in said data words having first and second input terminals and an output terminal, said output terminal of each of said logic circuits being connected individually to an input of a separate one of said stages of said parity word register; f. means coNnecting the output of each of said stages in said parity word register individually to the first of said input terminals of said logic circuit associated with that stage; and g. means for alternately connecting the outputs from the individual stages of said first and second registers to said second terminal of said logic circuit associated with the corresponding stage of said parity word register.
Claim 5
Dependent Claim
15 words
Apparatus as in claim 1 wherein said memory operates in a read before write cycle.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-06-02 | 1978-12-02 | 1979-06-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-06-02 | 1982-12-02 | 1983-06-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-06-02 | 1986-12-02 | 1987-06-03 | $7700.00 | Window Closed / Lapsed |