US3885134A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Binary-to-percent converter
Assignee: Honeywell Inc
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Filing: 1973-05-22
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Granted: 1975-05-20
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Expires: 1993-05-22
Abstract
Abstract A binary to binary percent converter has a first counter for storing a binary input signal and a clock means generating a clock signal which is selectively applied to the counter means to count down from the binary input signal to a zero store count level. A multiplier circuit is arranged to divide the clock signals supplied to the first counter by a predetermined fraction to convert the clock signal to a percent representation of the binary input signal. The percent representation is stored in a second counter and read out as a binary output signal.
Inventors
- 👤 William P Bergin
- 👤 Charles C Farmer
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 06:15
CPC Classifications
H; H03; H03M; H03M7/00
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
196 words
A converter circuit comprising: a counter means for storing an input data signal and responsive to a clock signal for counting from said data signal to a predetermined count, clock signal generating means, gate means connected between said clock signal generating means and said counter means to apply clock signals from said clock signal generating means to said counter means until said predetermined count is reached in said counter means, multiplier means for multiplying an input signal to said multiplier means by a predetermined factor, and means for applying said clock signals from said gate means as an input signal to said multiplier means to be multiplied by said predetermined factor to produce an output signal from said multiplier means having a predetermined relationship with respect to said input data signal to said counter means, said predetermined factor used by said multiplier means being 50/2n-1 where n is the number of bits in the input signal and said multiplier means including pulse adding means for adding one pulse for every other multiplication cycle of said multiplier means and averaging means for averaging four cycles of said multiplier means to produce an average multipling factor of 101/2n.
Claim 2
Dependent Claim
196 words
A converter circuit comprising: a counter means for storing an input data signal and responsive to a clock signal for counting from said data signal to a predetermined count, clock signal generating means, gate means connected between said clock signal generating means and said counter means to apply clock signals from said clock signal generating means to said counter means until said predetermined count is reached in said counter means, multiplier means for multiplying an input signal to said multiplier means by a predetermined factor, and means for applying said clock signals from said gate means as an input signal to said multiplier means to be multiplied by said predetermined factor to produce an output signal from said multiplier means having a predetermined relationship with respect to said input data signal to said counter means, said predetermined factor used by said multiplier means being 50/2n-1 where n is the number of bits in the input signal and said multiplier means including pulse adding means for adding one pulse for every other multiplication cycle of said multiplier means and averaging means for averaging four cycles of said multiplier means to produce an average multipling factor of 101/2n.
Claim 3
Dependent Claim
27 words
A converter circuit as set forth on claim 1 wherein said multiplier means includes a second counter means for storing said output signal from said multiplier means.
Claim 4
Dependent Claim
39 words
A converter circuit as set forth in claim 2 wherein said input signal to said first-mentioned counter means is a binary signal and an output signal from said second counter means in said multiplier circuit is a binary signal.
Claim 5
Dependent Claim
69 words
A converter circuit as set forth in claim 2 wherein said first-mentioned counter means is a seven bit binary counter and said input signal to said first-mentioned counter means is a seven bit binary signal and said output signal from said second counter circuit in said multiplier means is a binary signal and said multiplier circuit is arranged to multiply said binary input signal by a factor of 101/128.
Claim 6
Dependent Claim
35 words
A converter circuit as set forth in claim 1 wherein said gate means includes means responsive to a zero count level stored in said counter means to block said clock signals from said counter means.
Claim 7
Dependent Claim
37 words
A converter circuit as set forth in claim 1 wherein said data input signal is a seven bit binary signal and the predetermined factor used by said multiplier circuit is 50/6 4 and said factor is 101/128.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-05-19 | 1978-11-18 | 1979-05-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-05-19 | 1982-11-18 | 1983-05-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-05-19 | 1986-11-18 | 1987-05-20 | $7700.00 | Window Closed / Lapsed |