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US3884733A Expired / Lapsed US ⏱️ 0.0 years remaining

Dielectric isolation process

Assignee: Texas Instruments Inc
•
Filing: 1974-02-19
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Granted: 1975-05-20
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Expires: 1994-02-19
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Abstract

Abstract A method of epitaxially depositing onto a semiconductor substrate by planarizing the deposition surface of the substrate substantially parallel to a predetermined crystallographic plane, forming a deposition mask which exposes a predetermined site on the surface of the substrate, and epitaxially depositing semiconductor material in a preferred growth direction at the exposed site to produce a monocrystalline structure. A plurality of sites may be exposed through the deposition mask to permit formation of a plurality of discrete monocrystalline structures having predetermined spacing. Layers of different conductivity types can be formed in the structures by selective doping during deposition. Monocrystalline structures formed by the above method may be coated with a dielectric material and further processed to produce semiconductor devices for use in integrated circuits. If the monocrystalline structures are suitably arrayed and of a different conductivity type than the substrate, thus yielding semiconductor diodes, they can be utilized as a target in a vidicon tube.

Inventors

  • 👤 Kenneth Elwood Bean

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-26 17:31
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/20; H10D; H10D99/00; H10P; H10P14/00; H10P14/20; H10P14/24; H10P14/27; H10P14/271; H10P14/29; H10P14/2901; H10P14/2902; H10P14/2905; H10P14/2926; H10P14/34; H10P14/3402; H10P14/3404; H10P14/3411; H10W10/00; H10W10/01; H10W10/011; H10W10/018; H10W10/10; Y; Y10; Y10S; Y10S148/00; Y10S148/026; Y10S148/03; Y10S148/051; Y10S148/085; Y10S148/115; Y10S438/00; Y10S438/928

Claims Analysis

Total Claims: 8
Claim 1
Independent Claim 139 words
A METHOD FOR MANUFACTURE OF DIELECTRICALLY ISOLATED SEMICONDUCTOR DEVICES COMPRISING: A. PLANARIZING A MONOCRYSTALLINE SEMICONDUCTOR SUBSTRATE TO PROVIDE A SURFACE PARALLEL TO A SELECTED CRYSTALLOGRAPHIC PLANE; B. EPITAXIALLY DEPOSITING ASEMICONDUCTOR MATERIAL AT PREDETERMINED SITES ON SAID SUBSTRATE TO PROVIDE A PLURALITY OF DEPOSITED REGIONS, EACH HAVING AT LEAST ONE P-N JUNCTION THEREIN; C. FORMING A DIELECTRIC COATING ON THE DEPOSITED SEMICON- DUCTOR MATERIAL; D. DEPOSITING A REINFORCING MATERIAL ON THE DIELECTRIC COATING TO A DEPTH SUFFICIENT TO SUBSTANTIALLY FILL THE SPACES BETWEEN THE DEPOSITED REGIONS; E. REMOVING THE ORIGINAL SUBSTRATE TO EXPOSE SURFACE OF THE EPITAXIAL STRUCTURES; F. THEN PLANARIZING THEREINFORCED SURFACE OF THE STRUCTURE TO REEXPOSE THE OPPOSITE SURFACES OF THE EPITAXIAL STRUCTURES; AND G. THEN SELECTIVELY METALLIZING BOTH SURFACES OF THE COMPOSITE STRUCTURE TO ESTABLISH OHMIC CONTACT TO SELECTED PORTIONS OF BOTH SURFACES OF SAID EPITAXIAL STRUCTURES.
Claim 2
Independent Claim 139 words
A METHOD FOR MANUFACTURE OF DIELECTRICALLY ISOLATED SEMICONDUCTOR DEVICES COMPRISING: A. PLANARIZING A MONOCRYSTALLINE SEMICONDUCTOR SUBSTRATE TO PROVIDE A SURFACE PARALLEL TO A SELECTED CRYSTALLOGRAPHIC PLANE; B. EPITAXIALLY DEPOSITING ASEMICONDUCTOR MATERIAL AT PREDETERMINED SITES ON SAID SUBSTRATE TO PROVIDE A PLURALITY OF DEPOSITED REGIONS, EACH HAVING AT LEAST ONE P-N JUNCTION THEREIN; C. FORMING A DIELECTRIC COATING ON THE DEPOSITED SEMICON- DUCTOR MATERIAL; D. DEPOSITING A REINFORCING MATERIAL ON THE DIELECTRIC COATING TO A DEPTH SUFFICIENT TO SUBSTANTIALLY FILL THE SPACES BETWEEN THE DEPOSITED REGIONS; E. REMOVING THE ORIGINAL SUBSTRATE TO EXPOSE SURFACE OF THE EPITAXIAL STRUCTURES; F. THEN PLANARIZING THEREINFORCED SURFACE OF THE STRUCTURE TO REEXPOSE THE OPPOSITE SURFACES OF THE EPITAXIAL STRUCTURES; AND G. THEN SELECTIVELY METALLIZING BOTH SURFACES OF THE COMPOSITE STRUCTURE TO ESTABLISH OHMIC CONTACT TO SELECTED PORTIONS OF BOTH SURFACES OF SAID EPITAXIAL STRUCTURES.
Claim 3
Dependent Claim 23 words
A method as in claim 1 wherein the initial substrate is monocrystalline silicon planarized to provide a surface parallel to a (110) plane.
Claim 4
Dependent Claim 40 words
A method as in claim 1 wherein the epitaxial growth is controlled by doping to provide first regions of one conductivity type, and adjacent regions thereon of opposite conductivity type to provide a single p-n junction at each growth site.
Claim 5
Dependent Claim 59 words
A method as in claim 1 wherein said epitaxial growth is controlled by selective doping to provide a first region of one conductivity type at each site, covered by second regions of opposite conductivity type, covered by third regions of said one conductivity type, whereby the ultimate structure produced comprises a plurality of transistor devices interconnected by selective metallization.
Claim 6
Dependent Claim 22 words
A method as in claim 1 wherein said predetermined sites for epitaxial growth are defined by an apertured mask comprising silicon dioxide.
Claim 7
Dependent Claim 19 words
A method as in claim 1 wherein said semiconductor comprises silicon and wherein said reinforcing material comprises polycrystalline silicon.
Claim 8
Dependent Claim 75 words
A method as in claim 4 wherein said transistors are provided with ohmic contact by a sequence of steps comprising selective preferential etching through a region of one conductivity type to expose the intermediate region of opposite conductivity type; followed by the formation of an apertured window in the etched area and subsequent metallization to establish direct ohmic connection to the intermediate region, concurrently with metallization of the remaining two regions of the respective devices.

References Cited (Backward Citations)

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USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1978-05-19 1978-11-18 1979-05-20 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1982-05-19 1982-11-18 1983-05-20 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1986-05-19 1986-11-18 1987-05-20 $7700.00 Window Closed / Lapsed

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