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US3883802A
Expired / Lapsed
US
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Process for stress testing FET gates without the use of test patterns
Assignee: International Business Machines Corp
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Filing: 1973-12-14
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Granted: 1975-05-13
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Expires: 1993-12-14
Abstract
Abstract A testing process is described for stress testing each gate electrode in a dynamic random logic FET circuit array incorporated in an LSI device. The process comprises the steps of providing operating potentials and clock signals to each logic circuit in a logic path in the LSI device; providing a stress voltage to each initial logic element in a logic path, and sequencing the clock signals to each logic circuit in reverse order to that sequence required to transfer information through a logic path to perform the circuit logic function. The invention advantageously utilizes the fact a reverse clock will sequentially stress each logic circuit while in a discharge state and the other logic circuits are in a non-conducting condition.
Inventors
- 👤 Yogishwar Kumar Puri
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 19:18
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/316; G01R31/3161; G01R31/30
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
116 words
In a testing process for dynamic, random logic FET circuit arrays without the use of test patterns comprising the steps of a. providing a plurality of clock phases to each dynamic, random logic FET circuit in an array under test, the clock phases having a prescribed time relation to one another to transfer information through the array of logic circuits, b. providing operating potentials to each random logic FET circuit under test, c. providing an initial stress voltage to each random logic FET circuit in the array adapted to receive a data input, d. and cycling the clock phases in reverse order to the prescribed time relation for transferring information through the array of logic circuits.
Claim 2
Dependent Claim
116 words
In a testing process for dynamic, random logic FET circuit arrays without the use of test patterns comprising the steps of a. providing a plurality of clock phases to each dynamic, random logic FET circuit in an array under test, the clock phases having a prescribed time relation to one another to transfer information through the array of logic circuits, b. providing operating potentials to each random logic FET circuit under test, c. providing an initial stress voltage to each random logic FET circuit in the array adapted to receive a data input, d. and cycling the clock phases in reverse order to the prescribed time relation for transferring information through the array of logic circuits.
Claim 3
Dependent Claim
38 words
The invention of claim 1 wherein each FET logic circuit comprises a plurality of gating elements and the process further comprises the steps of a. providing sets of clock pulses to the gating elements in a logic circuit.
Claim 4
Dependent Claim
34 words
The invention of claim 2 wherein each logic circuit is characterized by a type number and the process further comprises the steps of a. providing different combinations of clock pulses to each logic circuit.
Claim 5
Dependent Claim
63 words
The invention of claim 3 wherein each FET device in a logic circuit includes a gate electrode and the process further comprises the steps of a. defining a plurality of logic types for the transfer of information through a logic circuit, b. and stressing gate electrodes for each FET device in a logic circuit as the clock phases are applied in reverse order.
Claim 6
Dependent Claim
21 words
The invention of claim 4 wherein the plurality is three logic types for the transfer of information through a logic circuit.
Claim 7
Dependent Claim
21 words
The invention of claim 4 wherein the plurality is four logic types for the transfer of information through a logic circuit.
Claim 8
Dependent Claim
21 words
The invEntion of claim 4 wherein the plurality is six logic types for the transfer of information through a logic circuit.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-05-12 | 1978-11-11 | 1979-05-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-05-12 | 1982-11-11 | 1983-05-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-05-12 | 1986-11-11 | 1987-05-13 | $7700.00 | Window Closed / Lapsed |