Patent US3882472A successfully refreshed from Google Patents.
US3882472A
Expired / Lapsed
US
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Data flow control in memory having two device memory cells
Assignee: Arris Technology Inc
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Filing: 1974-05-30
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Granted: 1975-05-06
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Expires: 1994-05-30
Abstract
Abstract Method and apparatus for controlling data flow in a memory comprised of a two device memory cell wherein the devices in the cell are connected through a storage node. A first command line is operably connected to the control terminal of the first device in the cell and the output circuit of the first device is connected between a data input-output line and the storage node. The second device in the cell has its output circuit connected between the data line and a second command line and its control terminal connected to the storage node. The storage node is charged to one of two discrete logic levels. To perform a read operation, the data line is precharged to a first voltage level and the second command line is precharged to a first voltage voltage level. The second device in the cell is effective, if rendered conductive by the charge on the storage node, to change the voltage level of the data line to the second voltage level such that the resulting voltage level on the data line is representative of the charge on the storage node, and therefore the data in the cell, which may then be read. In order to write data into the cell, the data line is charged to a voltage level representative of the data to be stored (which may be the resulting voltage if refreshing is to take place) and the first command line is charged to a first voltage level such that the first device is rendered conductive to charge the storage node to the voltage level present on the data line. A combination of a read cycle and a write cycle refreshes the cell without the necessity of a refresh amplifier.
Inventors
- 👤 Kent F Smith
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 04:44
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/403; G11C11/404
Claims Analysis
Total Claims: 24
Claim 1
Independent Claim
173 words
A method for controlling data flow into a two device memory cell wherein each of the devices have a control terminal and an output circuit, a first command line operably connected to the control terminal of the first device, a storage node, a single data input-output line, the output circuit of the first device being connected between said data line and said node, a second command line, the second device having its output circuit connected between said data line and said second command line and its control terminal connected to said node, the method comprising the steps of charging the node to a discrete logic level, precharging the data line to a first voltage level, charging the second command line to a second voltage level, the second device being effective, if rendered conductive by the charge on the storage node, to change the voltage level of the data line to the second voltage level such that the resulting voltage level on the data line is representative of the charge on the storage node.
Claim 2
Independent Claim
173 words
A method for controlling data flow into a two device memory cell wherein each of the devices have a control terminal and an output circuit, a first command line operably connected to the control terminal of the first device, a storage node, a single data input-output line, the output circuit of the first device being connected between said data line and said node, a second command line, the second device having its output circuit connected between said data line and said second command line and its control terminal connected to said node, the method comprising the steps of charging the node to a discrete logic level, precharging the data line to a first voltage level, charging the second command line to a second voltage level, the second device being effective, if rendered conductive by the charge on the storage node, to change the voltage level of the data line to the second voltage level such that the resulting voltage level on the data line is representative of the charge on the storage node.
Claim 3
Dependent Claim
61 words
The method of claim 1 further comprising the steps of charging the data line to a logic level representative of the data to be stored in the cell and charging the first command line to the first voltage level such that said first device is rendered conductive to charge the storage node to the logic level present on the data line.
Claim 4
Dependent Claim
23 words
The method of claim 2 wherein the step of charging the data line comprises retaining the resulting voltage level on the data line.
Claim 5
Dependent Claim
24 words
The method of claim 2 wherein the step of charging the data line comprises connecting the data line to the input of the memory.
Claim 6
Independent Claim
248 words
A method for controlling data flow in a memory having a plurality of two device memory cells aRranged in a row by column matrix, each row being associated with a single data input-output flow line and each column being associated with first and second command lines, each cell having a first device with a control terminal connected to the first command line associated with the cell, a storage node, the output circuit of the first device connected between the data line associated with the cell and the storage node, the output circuit of the second device connected between the data associated with the cell and the second command line associated with the cell and the control terminal thereof connected to the storage node, the method comprising the steps of charging the storage node to a discrete logic level, precharging each of the data lines to a first given voltage level, selecting the column of the cell to be addressed, charging the second command line in the addressed column to a second voltage level such that the second device in each cell in the addressed column is effective, if rendered conductive by the storage node connected thereto, to charge the voltage level of the data line of the row in which the cell is present to the second voltage level thereby causing the resulting voltage level on each data line to be representative of the logic level of the storage node of each cell respectively in the addressed column.
Claim 7
Independent Claim
248 words
A method for controlling data flow in a memory having a plurality of two device memory cells aRranged in a row by column matrix, each row being associated with a single data input-output flow line and each column being associated with first and second command lines, each cell having a first device with a control terminal connected to the first command line associated with the cell, a storage node, the output circuit of the first device connected between the data line associated with the cell and the storage node, the output circuit of the second device connected between the data associated with the cell and the second command line associated with the cell and the control terminal thereof connected to the storage node, the method comprising the steps of charging the storage node to a discrete logic level, precharging each of the data lines to a first given voltage level, selecting the column of the cell to be addressed, charging the second command line in the addressed column to a second voltage level such that the second device in each cell in the addressed column is effective, if rendered conductive by the storage node connected thereto, to charge the voltage level of the data line of the row in which the cell is present to the second voltage level thereby causing the resulting voltage level on each data line to be representative of the logic level of the storage node of each cell respectively in the addressed column.
Claim 8
Dependent Claim
83 words
The method of claim 5 further comprising the steps of charging the data line in the addressed row to a voltage level representative of the data to be stored on the addressed cell and charging the first command line in the addressed column to the first voltage level such that the first device in each cell of the addressed column is effective to charge the storage node of that cell to the voltage level present on the data line associated with that cell.
Claim 9
Dependent Claim
26 words
The method of claim 6 wherein the step of charging the data line comprises retaining the voltage level on the data lines in the nonaddressed rows.
Claim 10
Dependent Claim
28 words
The method of claim 7 wherein the step of charging the data line comprises connecting the data line of the addressed row to the input of the memory.
Claim 11
Dependent Claim
24 words
The method of claim 6 wherein the step of charging the data line comprises retaining the resulting voltage on each row of the memory.
Claim 12
Dependent Claim
180 words
A data flow control system for a memory of the type having a two device memory cell comprising a first command line, a second command line and a single data flow line, the control terminal on the first device being operably connected to said first command line, the output circuit of the first device being operably connected between said data line and the storage node of the cell, the storage node being operably connected to the control terminal of the second device and the output circuit of the second device being operably connected between said data line and said second command line, means for charging the storage node to a discrete logic level, means for precharging said data line to a first voltage level, means for charging said second command line to a second voltage level, said first and second voltage levels having a voltage level difference sufficient to render the second device conductive if the storage node is at a given logic level thereby causing the voltage level of the data line to change to the second voltage level.
Claim 13
Dependent Claim
180 words
A data flow control system for a memory of the type having a two device memory cell comprising a first command line, a second command line and a single data flow line, the control terminal on the first device being operably connected to said first command line, the output circuit of the first device being operably connected between said data line and the storage node of the cell, the storage node being operably connected to the control terminal of the second device and the output circuit of the second device being operably connected between said data line and said second command line, means for charging the storage node to a discrete logic level, means for precharging said data line to a first voltage level, means for charging said second command line to a second voltage level, said first and second voltage levels having a voltage level difference sufficient to render the second device conductive if the storage node is at a given logic level thereby causing the voltage level of the data line to change to the second voltage level.
Claim 14
Dependent Claim
39 words
The system of claim 10 further comprising means for charging said first command line to said first voltage level thereby rendering the first device conductive and causing the storage node to assume the logic level of said data line.
Claim 15
Dependent Claim
19 words
The system of claim 10 wherein said precharging means is always actuated before said second command line charging means.
Claim 16
Dependent Claim
22 words
The system of claim 11 wherein said second command line charging means is always actuated before said first command line actuating means.
Claim 17
Dependent Claim
44 words
The system of claim 10 further comprising means for charging said data line in accordance with the data input of the circuit, said data line charging means being effective to overpower any voltage level present on said data Line prior to the actuation thereof.
Claim 18
Dependent Claim
25 words
The system of claim 10 further comprising means for sensing the logic level on said data line after said second command line has been actuated.
Claim 19
Independent Claim
266 words
A system for controlling data flow in a memory having a plurality of two device memory cells arranged in a row and column matrix array comprising a single data flow line associated with each row of cells and a first and a second command line associated with each column of cell, the first device in each cell having a control terminal operably connected to said first command line of the column in which the cell is situated and an output circuitry operably connected between said data line in the row in which the cell is situated and the storage node of the cell, the control terminal of the second device of each cell being operably connected to the storage node of that cell and the output circuit of the second device being operably connected between the data line of the row in which the cell is situated and said second command line of the column in which the cell is situated, means for charging each storage node to a discrete logic level, means for precharging each of said data lines to a first voltage level, means for charging said second comnand line of the addressed column to a second voltage level, said first and second voltage levels having a voltage level difference sufficient to render conductive the second device of each cell in the addressed column if the storage node associated therewith is at a given logic level thereby causing the resulting voltage level on each of said data lines to be representative of the logic level of the respective storage nodes in the addressed column.
Claim 20
Independent Claim
266 words
A system for controlling data flow in a memory having a plurality of two device memory cells arranged in a row and column matrix array comprising a single data flow line associated with each row of cells and a first and a second command line associated with each column of cell, the first device in each cell having a control terminal operably connected to said first command line of the column in which the cell is situated and an output circuitry operably connected between said data line in the row in which the cell is situated and the storage node of the cell, the control terminal of the second device of each cell being operably connected to the storage node of that cell and the output circuit of the second device being operably connected between the data line of the row in which the cell is situated and said second command line of the column in which the cell is situated, means for charging each storage node to a discrete logic level, means for precharging each of said data lines to a first voltage level, means for charging said second comnand line of the addressed column to a second voltage level, said first and second voltage levels having a voltage level difference sufficient to render conductive the second device of each cell in the addressed column if the storage node associated therewith is at a given logic level thereby causing the resulting voltage level on each of said data lines to be representative of the logic level of the respective storage nodes in the addressed column.
Claim 21
Dependent Claim
81 words
The system of claim 16 further comprising means for charging said data line of the addressed row in accordance with the logic level to be stored in the addressed cell and charging said first command line in the addressed column to said first voltage level thus rendering conductive the first device in each cell in the addressed column such that the logic level present on each data line is assumed by the storage node on each cell in the addressed column.
Claim 22
Dependent Claim
20 words
The system of claim 17 wherein the resulting voltage level is retained on the data lines in the nonaddressed row.
Claim 23
Dependent Claim
22 words
The system of claim 18 further comprising means for connecting said data line charging means with the data input of the memory.
Claim 24
Dependent Claim
23 words
The system of claim 17 wherein the resulting voltage level is retained on all the data lines in each row of the memory.
References Cited (Backward Citations)
US3646525A
Cited
US3706079A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-05-05 | 1978-11-04 | 1979-05-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-05-05 | 1982-11-04 | 1983-05-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-05-05 | 1986-11-04 | 1987-05-06 | $7700.00 | Window Closed / Lapsed |