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US3882469A
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US
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Non-volatile variable threshold memory cell
Assignee: Texas Instruments Inc
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Filing: 1973-06-18
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Granted: 1975-05-06
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Expires: 1993-06-18
Abstract
Abstract Disclosed is a method which utilizes an insulated gate fieldeffect semiconductor device having a gate isolation comprised of at least two different gate isolation materials as a programmable non-volatile memory. Writing into the memory is accomplished by increasing the threshold voltage from its intrinsic device level to a second more positive level by trapping charges of one polarity in the gate isolation layers. Erasing the memory is accomplished by injecting into the gate isolation layers charges of opposite polarity, thereby neutralizing the previously stored charge and causing the modified device threshold voltage to return to substantially the intrinsic value.
Inventors
- 👤 Jr William Milton Gosney
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 08:26
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/60; H10D84/65; G; G11; G11C; G11C16/00; G11C16/02; G11C16/04; G11C16/0466; H10D30/00; H10D30/60; H10D30/69
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
218 words
In the operation of a non-volatile memory cell comprising an insulated gate field-effect semiconductor device having a source and drain and having a gate isolation means including two gate isolation materials, one of which is characterized by the ability to preferentially trap charges of one polarity, the other being characterized by the ability to preferentially trap charges of the opposite polarity, the improved method comprising the steps of: a. writing into the memory cell by increasing the positive voltage on the drain junction to a level which causes avalanche breakdown, while simultaneously applying a small voltage of source polarity to the gate terminal, thereby driving some of the avalanching carriers through only one of said gate isolation materials whereby a trapped charge is stored at the interface between the two gate isolation materials; then at an appropriate later time b. erasing the memory cell by increasing the voltage on the gate to a sufficiently high level to initiate injection of charges of opposite polarity from the gate electrode into the isolation layers, while holding the source, drain and substrate electrodes at substantially ground potential, thereby causing said injection to occur preferentially at the interface between the gate isolation layers, whereby the stored charge at that location is neutralized to restore the threshold voltage to substantially its intrinsic value.
Claim 2
Dependent Claim
218 words
In the operation of a non-volatile memory cell comprising an insulated gate field-effect semiconductor device having a source and drain and having a gate isolation means including two gate isolation materials, one of which is characterized by the ability to preferentially trap charges of one polarity, the other being characterized by the ability to preferentially trap charges of the opposite polarity, the improved method comprising the steps of: a. writing into the memory cell by increasing the positive voltage on the drain junction to a level which causes avalanche breakdown, while simultaneously applying a small voltage of source polarity to the gate terminal, thereby driving some of the avalanching carriers through only one of said gate isolation materials whereby a trapped charge is stored at the interface between the two gate isolation materials; then at an appropriate later time b. erasing the memory cell by increasing the voltage on the gate to a sufficiently high level to initiate injection of charges of opposite polarity from the gate electrode into the isolation layers, while holding the source, drain and substrate electrodes at substantially ground potential, thereby causing said injection to occur preferentially at the interface between the gate isolation layers, whereby the stored charge at that location is neutralized to restore the threshold voltage to substantially its intrinsic value.
Claim 3
Dependent Claim
17 words
A method as in claim 1 wherein said insulated gate field-effect device is an n-channel MNOS IGFET.
Claim 4
Dependent Claim
32 words
The method of claim 1 wherein said trapped charges are electrons and said neutralizing charges are holes, said holes being injected into the gate region by Schottky injection from the gate contact.
Claim 5
Dependent Claim
43 words
A method as in claim 1 wherein said gate isolation means consists essentially of a silicon oxide layer adjacent the semiconductor, covered by a silicon nitride layer, said oxide layer having a thickness substantially greater than any thickness that would permit electron tunneling.
Claim 6
Dependent Claim
16 words
A method as in claim 4 wherein the thickness of said oxide is about 800 Angstroms.
References Cited (Backward Citations)
US3733591A
Cited
US3720925A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-05-05 | 1978-11-04 | 1979-05-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-05-05 | 1982-11-04 | 1983-05-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-05-05 | 1986-11-04 | 1987-05-06 | $7700.00 | Window Closed / Lapsed |