Memory system using variable threshold transistors

Claim 2

The combination of: an array of field-effect devices, arranged in columns and rows and sharing a common substrate, each device having a control electrode and first and second electrodes defining a conduction path, and each device of the type capable of assuming two threshold levels, the devices of each row having their conduction paths connected between a different pair of bit lines and the devices of each column having their control electrodes connected to a different word line; a plurality of single pole double throw switch means, one per bit line, each switch means directly connecting its bit line to either one of first and second potentials; means for setting, the threshold level of a device to one of said two threshold levels including means for operating the switch means to apply to each bit line said first potential and for concurrently applying to selected word lines a first voltage of greater than a given reference value with respect to said first potential in a direction to inhibit conduction of the devices; and means for setting, a column at a time, selected ones of said devices to the other one of said two threshold levels including means for connecting the switch means associated with the two bit lines of the selected transistors to said first potential and the switch means associated with the two bit lines of the non-selected transistors to said second potential and for concurrently applying to the word line of the selected transistors a second voltage of greater than a given reference value with respect to said first potential in a direction to cause conduction of the selected transistors, the magnitude of said second voltage and said second potential being approximately equal.

Claim 3

The combination of: an array of field-effect devices, arranged in columns and rows and sharing a common substrate, each device having a control electrode and first and second electrodes defining a conduction path, and each device of the type capable of assuming two threshold levels, the devices of each row having their conduction paths connected between a different pair of bit lines and the devices of each column having their control electrodes connected to a different word line; a plurality of single pole double throw switch means, one per bit line, each switch means directly connecting its bit line to either one of first and second potentials; means for setting, the threshold level of a device to one of said two threshold levels including means for operating the switch means to apply to each bit line said first potential and for concurrently applying to selected word lines a first voltage of greater than a given reference value with respect to said first potential in a direction to inhibit conduction of the devices; and means for setting, a column at a time, selected ones of said devices to the other one of said two threshold levels including means for connecting the switch means associated with the two bit lines of the selected transistors to said first potential and the switch means associated with the two bit lines of the non-selected transistors to said second potential and for concurrently applying to the word line of the selected transistors a second voltage of greater than a given reference value with respect to said first potential in a direction to cause conduction of the selected transistors, the magnitude of said second voltage and said second potential being approximately equal.

Claim 4

The combination of: an array of field-effect devices, arranged in columns and rows and sharing a common substrate, each device having a control electrode and first and second electrodes defining a conduction path, and each device of the type capable of assuming two threshold levels, the devices of each row having their conduction paths connected between a different pair of bit lines and the devices of each column having their control electrodes connected to a different word line; a plurality of single pole double throw switch means, one per bit line, each switch means directly connecting its bit line to either one of first and second potentials; means for setting, the threshold level of a device to one of said two threshold levels including means for operating the switch means to apply to each bit line said first potential and for concurrently applying to selected word lines a first voltage of greater than a given reference value with respect to said first potential in a direction to inhibit conduction of the devices; and means for setting, a column at a time, selected ones of said devices to the other one of said two threshold levels including means for connecting the switch means associated with the two bit lines of the selected transistors to said first potential and the switch means associated with the two bit lines of the non-selected transistors to said second potential and for concurrently applying to the word line of the selected transistors a second voltage of greater than a given reference value with respect to said first potential in a direction to cause conduction of the selected transistors, the magnitude of said second voltage and said second potential being approximately equal.

Claim 5

The combination as claimed in claim 1 wherein said common substrate is maintained at said first potential.

Claim 6

The combination as claimed in claim 1 wherein said first potential is ground potential; wherein one of said first and second voltages is more positive than said ground potential and the other of said first and second voltages is more negative than said ground potential; and wherein said ground potential is applied to said common substrate.

Claim 7

The combination as claimed in claim 1 wherein each one of said switch means includes a first transistor for clamping said bit line to one of said two potentials and a second transistor for clamping said bit line to the other one of said two potentials.

Claim 8

The combination as claimed in claim 4 wherein said devices capable of assuming two threshold levels are field-effect transistors having a second insulator layer in addition to the oxide layer between the gate and the substrate.

Claim 9

In combination: a matrix array of bistable insulated gate field-effect transistors directly connected to a common substrate arranged in rows and columns, and having two bit lines per row and one word line per column, each transistor having a control electrode and first and second electrodes defining the ends of a conduction path; the conduction path of the transistors of each row being coupled between the first and second bit lines associated with that row and the transistors of a column having their control electrode connected in common to the word line associated with that column, each transistor being of the type which in response to a first voltage of greater than a given reference value applied between its control electrode and its substrate in a direction to cause conduction exhibits a first threshold level and which in response to a second voltage of greater than a given reference value applied between its control electrode and its substrate in a direction to inhibit conduction exhibits a seconD threshold level; a single pole double throw switch per bit line, each switch having a common electrode connected to said bit line, having a normally closed contact connected to a reference potential and a normally open contact connected to a first potential; means for setting the transistors of said matrix to said second threshold level including means for applying said reference potential to said substrate and through said switches to the bit lines and including means for applying a potential, substantially equal in magnitude and direction to said second voltage, to the word lines; and means for then setting selected ones of said transistors, one column at a time, to said first threshold level including means for applying said first potential substantially equal in magnitude and direction to said first voltage to their associated word line and means for maintaining the switches associated with the two bit lines of the selected transistors in their normally closed condition and for switching the switches associated with the bit lines of the non-selected transistors to the normally open condition.

Claim 10

In combination: a matrix array of bistable insulated gate field-effect transistors directly connected to a common substrate arranged in rows and columns, and having two bit lines per row and one word line per column, each transistor having a control electrode and first and second electrodes defining the ends of a conduction path; the conduction path of the transistors of each row being coupled between the first and second bit lines associated with that row and the transistors of a column having their control electrode connected in common to the word line associated with that column, each transistor being of the type which in response to a first voltage of greater than a given reference value applied between its control electrode and its substrate in a direction to cause conduction exhibits a first threshold level and which in response to a second voltage of greater than a given reference value applied between its control electrode and its substrate in a direction to inhibit conduction exhibits a seconD threshold level; a single pole double throw switch per bit line, each switch having a common electrode connected to said bit line, having a normally closed contact connected to a reference potential and a normally open contact connected to a first potential; means for setting the transistors of said matrix to said second threshold level including means for applying said reference potential to said substrate and through said switches to the bit lines and including means for applying a potential, substantially equal in magnitude and direction to said second voltage, to the word lines; and means for then setting selected ones of said transistors, one column at a time, to said first threshold level including means for applying said first potential substantially equal in magnitude and direction to said first voltage to their associated word line and means for maintaining the switches associated with the two bit lines of the selected transistors in their normally closed condition and for switching the switches associated with the bit lines of the non-selected transistors to the normally open condition.

Claim 11

In combination: an array of metal-nitride-oxide semiconductors (MNOS) memory devices arranged in columns and rows, each device having a conduction path and a gate electrode; a plurality of column conductors, each column conductor connected to the gate electrodes of all devices in that column; a plurality of pairs of row conductors, each pair connected across the conduction paths of all devices in its row; means for placing the devices in a selected column in one state comprising means for placing all of the row conductors at ground and means for placing the conductor for that column at a voltage level to inhibit conduction through the devices in that column; and means for changing the state of a device in the selected column and in a selected row to a second state comprising means for applying to that column conductor a voltage in a sense to enhance conduction through all devices in that column, means for placing the pair of conductors in the selected row at ground, and means for applying to the remaining pairs of row conductors a voltage of the same polarity and approximately the same value as applied to the selected column conductor.

Claim 12

In combination: an array of metal-nitride-oxide semiconductors (MNOS) memory devices arranged in columns and rows, each device having a conduction path and a gate electrode; a plurality of column conductors, each column conductor connected to the gate electrodes of all devices in that column; a plurality of pairs of row conductors, each pair connected across the conduction paths of all devices in its row; means for placing the devices in a selected column in one state comprising means for placing all of the row conductors at ground and means for placing the conductor for that column at a voltage level to inhibit conduction through the devices in that column; and means for changing the state of a device in the selected column and in a selected row to a second state comprising means for applying to that column conductor a voltage in a sense to enhance conduction through all devices in that column, means for placing the pair of conductors in the selected row at ground, and means for applying to the remaining pairs of row conductors a voltage of the same polarity and approximately the same value as applied to the selected column conductor.

Claim 13

In combination: an array of field effect memory devices capable of assuming two states arranged in columns and rows, each device having a conduction path and a gate electrode; a plurality of column conductors, each column conductor connected to the gate electrodes of all devices in that column; a plurality of pairs of row conductors, each pair connected across the conduction paths of all devices in its row; means for placing devices in a selected column in one state comprising means for placing the row conductors for said devices at the same potential and means for placing the conductor for that column at a voltage level greater than a given first value and in a sense to inhibit conduction through said devices in that column; and means for changing the state of at least one device in the selected column and in a selected row to its second state comprising means for applying to the selected column conductor a voltage greater than a predetermined second value in a sense to enhance conduction through all devices in that column, means for placing the pair of conductors in the selected row at a reference level, and means for applying to the row conductors for nonselected devices a voltage of the same polarity and approximately the same value as applied to the column conductors.

Claim 14

In combination: an array of field effect memory devices capable of assuming two states arranged in columns and rows, each device having a conduction path and a gate electrode; a plurality of column conductors, each column conductor connected to the gate electrodes of all devices in that column; a plurality of pairs of row conductors, each pair connected across the conduction paths of all devices in its row; means for placing devices in a selected column in one state comprising means for placing the row conductors for said devices at the same potential and means for placing the conductor for that column at a voltage level greater than a given first value and in a sense to inhibit conduction through said devices in that column; and means for changing the state of at least one device in the selected column and in a selected row to its second state comprising means for applying to the selected column conductor a voltage greater than a predetermined second value in a sense to enhance conduction through all devices in that column, means for placing the pair of conductors in the selected row at a reference level, and means for applying to the row conductors for nonselected devices a voltage of the same polarity and approximately the same value as applied to the column conductors.