Voltage translation circuit for mnos memory array

Claim 2

In combination; an input terminal and an output terminal; means for applying to said input terminal a voltage which is at one of two levels; means responsive to a first control voltage for providing a low impedance path between said two terminals; means responsive to the presence of a second control voltage and the absence of said first control voltage for applying the complement of the voltage present at said input terminal to said output terminal and for opening said low impedance path; and means responsive to a third control voltage and the absence of said first and second control voltages for providing a first conduction path between said terminals and a second conduction path between said output terminal and a point of reference potential.

Claim 3

In the combination as set forth in claim 1, said first and second conduction paths each comprising the conduction path of a field-effect transistor and each exhibiting a different resistance.

Claim 4

the first and second switches closed and the third switch open; and

Claim 5

the first and second switches closed and the third switch open; and

Claim 6

the third switch closed and the first and second switches open.

Claim 7

the third switch closed and the first and second switches open.

Claim 8

In the combination as set forth in claim 1, said means responsive to the presence of said second control voltage and the absence of said first control voltage comprising: two field-effect transistors the conduction paths of which are connected in series between said output terminal and a point of reference potential, the first said transistor being directly connected to said output terminal and whose conduction path is placed in a low impedance condition in response to the presence of said second control voltage and the second said transistor having a conduction path whose impedance is responsive to the value of the signal present at said input terminal, being relatively high when said signal is of one value and being relatively low when said signal is at its other value; and a voltage source of value approximately equal to the level at said input terminal which places said second transistor in a low impedance condition, connected to the connection between the conduction paths of said first and second transistors.

Claim 9

In combination; a first switch which exhibits a given resistance when it conducts connected between an input terminal and an output terminal; a second switch which exhibits a relatively lower resistance when it conducts, connected between said output terminal and ground; a third switch which exhibits said given resistance when it conducts connected between a terminal for receiving an operating voltage and said output terminal; a fourth switch which exhibits said given resistance when it conducts controlled by the voltage present on said input terminal and connected between said terminal for said operating voltage and ground; and means for causing said switches to assume the following states:

Claim 10

In combination; a first switch which exhibits a given resistance when it conducts connected between an input terminal and an output terminal; a second switch which exhibits a relatively lower resistance when it conducts, connected between said output terminal and ground; a third switch which exhibits said given resistance when it conducts connected between a terminal for receiving an operating voltage and said output terminal; a fourth switch which exhibits said given resistance when it conducts controlled by the voltage present on said input terminal and connected between said terminal for said operating voltage and ground; and means for causing said switches to assume the following states:

Claim 11

In combination: a first field-effect transistor the conduction path of which is connected between an input terminal and an output terminal; a second field-effect transistor of substantially higher gain than the first, the conduction path of which is connected between said output terminal and ground; a third field-effect transistor the condUction path of which is connected between said output terminal and a source of operating potential; a fourth field-effect transistor the conduction path of which is connected between said source of operating potential and ground; means for placing the conduction path of said first transistor in its low impedance condition while the conduction paths of the second and third transistors are in their high impedance state; means for concurrently placing the conduction paths of said first and second transistors in their low impedance condition while the conduction path of said third transistor is in its high impedance state; and means for placing the conduction path of said third transistor in its low impedance condition while the conduction paths of said first and second transistors are in their high impedance condition and concurrently controlling the impedance of the conduction path of said fourth transistor in response to the voltage present at said input terminal.

Claim 12

In combination: a first field-effect transistor the conduction path of which is connected between an input terminal and an output terminal; a second field-effect transistor of substantially higher gain than the first, the conduction path of which is connected between said output terminal and ground; a third field-effect transistor the condUction path of which is connected between said output terminal and a source of operating potential; a fourth field-effect transistor the conduction path of which is connected between said source of operating potential and ground; means for placing the conduction path of said first transistor in its low impedance condition while the conduction paths of the second and third transistors are in their high impedance state; means for concurrently placing the conduction paths of said first and second transistors in their low impedance condition while the conduction path of said third transistor is in its high impedance state; and means for placing the conduction path of said third transistor in its low impedance condition while the conduction paths of said first and second transistors are in their high impedance condition and concurrently controlling the impedance of the conduction path of said fourth transistor in response to the voltage present at said input terminal.