Digital frequency correlator

Claim 2

A digital frequency correlator circuit for digitally comparing the frequencies of a plurality of a-c signals to determine if they are coherent within a predetermined number of cycles comprising: a. means for providing a plurality of first a-c signals; b. means for receiving said plurality of first a-c signals and converting each of said first a-c signals into a digital number representing the frequency of each first a-c signal; c. means for generating and providing control signals to said means for providing a plurality of first a-c signals and to said means for converting each of said first a-c signals into a digital number representing the frequency of each first a-c signal, said control signals synchronizing the operation of said means for providing a plurality of first a-c signals and said means for converting each of said first a-c signals into a digital number representing the frequency of each first a-c signal; d. means for receiving each said digital number and comparing each said digital number with each other said digital number and outputting a logic 0 whenever any comparision of two said digital numbers exceeds a predetermined number of cycles and outputting a logic 1 whenever any comparison of two said digital numbers is equal to or less than a predetermined number of cycles, said means having a separate output for each said comparison.

Claim 3

The digital frequency correlator circuit of claim 1 wherein said means for receiving and comparing each said digital number with each other said digital number with each other said digital number comprises: a. means for receiving each said digital number and for digitally subtracting each said digital number from each other said digital number, thereby obtaining a digital representation of the difference in cycles of each said first a-c signal from each other said first a-c signal, each said digital representation including a carry bit; b. means for receiving each said digital representation of the difference in cycles and comparing each said digital representation of the difference in cycles with a predetermined number of cycles, said means having one output for each comparison, said means outputting a logic 1 for each comparison where said difference in cycles in equal to or less than said predetermined number of cycles or a logic 0 for each comparison where said difference in cycles is greater than said predetermined number of cycles.

Claim 4

The digital frequency correlator circuit of claim 2 wherein said means for receiving and digitally subtracting each said digital number from each other said digital number includes: means for complementing one of each two digital numbers to be subtracted and digitally adding said complemented digital number to said uncomplemented digital number, said means outputting a plurality of said digital representations of the difference in cycles of each said first a-c signal for each other said first a-c signal including a carry bit for each said digital representation.

Claim 5

The digital frequency correlator circuit of claim 2 wherein said means for receiving and comparing each said digital representtion of the difference in cycles with a predetermined number of cycles includes: a. a plurality of exclusive-or circuits each containing a plurality of exclusive-or gates, each said exclusive-or circuit receiving one digital representation less a predetermined number of least significant bits of said digital representation and said carry, said plurality of exclusive-or gates being equal in number to the number of bits of said digital representation received by said exclusive-or circuit, each said exclusive-or gate being inputted by said carry-bit and one of said bits of said digital representation received by said exclusive-or circuit, each said exclusive-or gate having an output; and b. a plurality of AND-gates equal in number to said plurality of exclusive-or circuits, each AND-gate having an output and being inputted by the outputs of all exclusive-or gates of each exclusive-or circuit, said output of each AND-gate being a logic 1 when said digital representation is equal to or less than a predetermined number of cycles and a logic 0 when said digital representation is greater than a predetermined number of cycles, said predetermined number of cycles being equal to the binary digital value of said predetermined number of least significant bits of said digital representation not inputted to said exclusive-or circuits.

Claim 6

The digital frequency correlator circuit of claim 1 wherein said means for generating control signals comprises: a. means for providing a constant low-frequency signal having an output; b. means for generating an enable signal, a reset signal, and a shift signal having an enable signal output, a reset signal output, a shift signal output, and an input, said input being connected to said output of saiD means for providing a constant low-frequency signal, said enable signal allowing, when at a logic 1 level, or inhibiting, when at a logic 0 level, the passage of said plurality of first a-c signals from said means for providing a plurality of first a-c signals to said means for converting each of said first a-c signals into a digital number representing the frequency of each first a-c signal.

Claim 7

The digital frequency correlator circuit of claim 5 wherein said means for generating an enable signal, a reset signal, and a shift signal comprises: a flip-flop having an input, an enable signal output, and a shift signal output, said input being connected to said output of said means for providing a low-frequency signal; and b. a monostable multivibrator having an input and a reset signal output, said input being connected to said shift signal output of said flip-flop whereby said low-frequency signal drives said flip-flop, thereby generating an enable signal and a shift signal, said shift signal driving said monostable multivibrator, thereby generating said reset signal.

Claim 8

The digital frequency correlator circuit of claim 5 wherein said means for providing a plurality of first a-c signals comprises: a. means for providing a plurality of second a-c signals; b. means for providing a gate signal; c. means for receiving said gate signal and said plurality of second a-c signals and outputting one of a plurality of predetermined sequences of said second a-c signals, depending on the voltage level of said gate signal; and d. a gate circuit for receiving said predetermined sequence of second a-c signals and said enable signal, said gate circuit outputting said predetermined sequence when said enable signal is a logic 1 level, and inhibiting said predetermined sequence wkhen said enable signal is a logic 0 level, said predetermined sequence of second a-c signals being said plurality of first a-c signals.

Claim 9

The digital frequency correlator circuit of claim 7 wherein said means for providing a plurality of second a-c signals includes: a. means for providing a third a-c signal; and b. means for receiving and multiplying the frequency of said third a-c signal by a ratio of whole numbers wherein the absolute value of the numerator of said ratio is greater than the absolute value of the denominator of said ratio and greater than one, said means outputting said frequency-multiplied third a-c signal, said frequency-multiplied third a-c signal being one of said plurality of second a-c signals.

Claim 10

The digital frequency correlator circuit of claim 8 wherein said means for receiving and multiplying the frequency of said third a-c signal by a ratio of whole numbers comprises: a. means for providing a clock frequency signal of frequency greater than said third a-c signal having an output; b. means for receiving and dividing the frequency of said third a-c signal by a first whole number greater than one having an output; c. means for outputting a predetermned second whole number, greater than said first whole number, of cycles of said clock frequency signal for each cycle of said frequency-divided third a-c signal, said means for outputting having a clock-frequency-signal input, a second input, and an output, said clock frequency input being connected to said output of said means for providing a clock-frequency-signal, said second input being connected to said output of said means for receiving and dividing the frequency of said third a-c signal, said output being one of said plurality of second a-c signals.

Claim 11

The digital frequency correlator circuit of claim 9 wherein said means for outputting a predetermined second whole number of cycles of said clock-frequency-signal for each cycle of said frequency-divided third a-c signal comprises: a. a different circuit having an input and an output, said input being connected to said output of said means for receiving and dividing the frequency of said third a-c signal by a first whole number greater than one; b. a clock gate circuit having a lock frequency signal input, a second input and an output, said clock frequency signal input being connected to said output of said means for providing a clock frequency signal; c. a binary counter circuit having a first input, a second input, a first output, and a second output, said second input being connected to said output of said differentiator circuit, said first input being connected to said output of said clock gate circuit, said first output being said output of said means for outputting a predetermined second whole number of cycles of said clock frequency signal for each cycle of said frequency-divided third a-c signal; and d. a flip-flop circuit having a first input, a second input, and an output, said first input being connected to said second output of said binary counter circuit, said second input being connected to said output of said differentiator circuit, said output of said flip-flop circuit being connected to said second input of said clock gate circuit, whereby the signal on the output of said differentiator circuit resets said binary counter circuit and said flip-flop circuit, then said flip-flop circuit enables said clock gate circuit, passing said clock frequency signal to said binary counter circuit after counting said predetermined second whole number of cycles of said clock frequency signal, said binary counter circuit clocks said flip-flop circuit, causing said flip-flop circuit to inhibit said clock gate circuit until said differentiator circuit resets said binary counter circuit and said flip-flop circuit, thereby for every cycle of said frequency-divided third a-c signal a predetermined whole number of cycles of said clock frequency signal is outputted.

Claim 12

The digital frequency correlator circuit of claim 5 wherein said means for receiving said plurality of first a-c signals and converting each of said first a-c signals into a digital number representing the frequency of each first a-c signal comprises: a. a plurality of counter circuits, each counter circuit receiving one said first a-c signal, said plurality of counter circuits having a reset signal input connected to said reset signal output of said means for generating control signals, each said counter circuit having a plurality of outputs representing the frequency of each said first a-c signal in digital form; and b. a plurality of shift registers equal in number to said plurality of counter circuits, said plurality of shift registers having a shift signal input connected to said shift signal output of said means for generating control signals, each said shift register having a plurality of inputs equal in number and connected in parallel with each said plurality of outputs of each said counter circuit, each said shift register having a plurality of outputs equal in number to said plurality of inputs of each said shift register, said plurality of outputs of each said shift register being said digital number representing the frequency of each first a-c signal whereby said reset signal resets said plurality of counter circuits, then said enable signal assumes a logic 1 level, passing said plurality of first a-c signals to said plurality of counter circuits, then said enable signal assumes a logic 0 level, inhibiting the passage of said plurality of first a-c signals while said shift signal causes the contents of said plurality of counter circuits to be shifted into said plurality of shift registers.