US3879230A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor device diffusion source containing as impurities AS and P or B
Assignee: Toshiba Corp
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Filing: 1973-09-26
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Granted: 1975-04-22
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Expires: 1993-09-26
Abstract
Abstract A semiconductor device comprising a high impurity concentration region, the impurity consisting of arsenic and at least one impurity other than arsenic. The number of atoms of the arsenic is smaller than that of the other impurity.
Inventors
- 👤 Masakatsu Nakamura
- 👤 Toshio Yonezawa
- 👤 Taketoshi Kato
- 👤 Masaharu Watanabe
- 👤 Minoru Akatsuka
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 02:39
CPC Classifications
H; H10; H10D; H10D62/00; H10D62/80; H10D62/83; H10D62/834; H10P; H10P32/00; H10P32/10; H10P32/14; H10P32/1408; H10P32/141; H10P32/17; H10P32/171; H10P95/00; Y; Y10; Y10S; Y10S148/00; Y10S148/04; Y10S148/097; Y10S148/151; Y10S252/00; Y10S252/95; Y10S438/00; Y10S438/938
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
111 words
SEMICONDUCTOR DIFFUSION SOURCE FOR USE IN MANUFACTURING A SEMICONDUCTOR DEVICE HAVING A SEMICONDUCTOR SUBSTRATE TO FORM A HIGHLY DOPED SURFACE REGION IN SAID SUBSTRATE OF SAID FORM A HIGHLY SURFACE REGION IN SAID SUBSTRATE OF SAID SEMICONDUCTOR DEVICE, SAID SOURCE COMPRISING: A. A FIRST COMPONENT PHOSPHORUS OR BORON; AND B. A SECOND COMPONENT OF ARSENIC TO COMPENSATE FOR A LATTICE STRAIN CAUSED BY SAID FIRST COMPONENT WHEN SAID FIRST COMPONENT IS DIFFUSED AS AN IMPURITY INTO A SEMICONDUCTOR SUBSTRATE SAID FIRST SECOND COMPONENTS BEING IN AMOUNTS SUCH THAT THE CONCENTRATION OF THE SECOND IMPURITY IS SMALLER THAN THAT OF THE FIRST IMPURITY AT THE SURFACE OF SAID HIGHLY DOPED SURFACE REGION.
Claim 2
Dependent Claim
111 words
SEMICONDUCTOR DIFFUSION SOURCE FOR USE IN MANUFACTURING A SEMICONDUCTOR DEVICE HAVING A SEMICONDUCTOR SUBSTRATE TO FORM A HIGHLY DOPED SURFACE REGION IN SAID SUBSTRATE OF SAID FORM A HIGHLY SURFACE REGION IN SAID SUBSTRATE OF SAID SEMICONDUCTOR DEVICE, SAID SOURCE COMPRISING: A. A FIRST COMPONENT PHOSPHORUS OR BORON; AND B. A SECOND COMPONENT OF ARSENIC TO COMPENSATE FOR A LATTICE STRAIN CAUSED BY SAID FIRST COMPONENT WHEN SAID FIRST COMPONENT IS DIFFUSED AS AN IMPURITY INTO A SEMICONDUCTOR SUBSTRATE SAID FIRST SECOND COMPONENTS BEING IN AMOUNTS SUCH THAT THE CONCENTRATION OF THE SECOND IMPURITY IS SMALLER THAN THAT OF THE FIRST IMPURITY AT THE SURFACE OF SAID HIGHLY DOPED SURFACE REGION.
Claim 3
Dependent Claim
102 words
Semiconductor diffusion source for use in manufacturing a semiconductor device having a semiconductor substrate to form a highly doped surface region in said substrate of said semiconductor device, said source comprising: a. a first component phosphorus or boron; and b. a second component of arsenic to compensate for a lattice strain caused by said first component when said first component is diffused as an impurity into a semiconductor substrate said first and second components being in amounts such that the concentration of the second impurity is smaller than that of the first impurity at the surface of said highly doped surface region.
Claim 4
Dependent Claim
102 words
Semiconductor diffusion source for use in manufacturing a semiconductor device having a semiconductor substrate to form a highly doped surface region in said substrate of said semiconductor device, said source comprising: a. a first component phosphorus or boron; and b. a second component of arsenic to compensate for a lattice strain caused by said first component when said first component is diffused as an impurity into a semiconductor substrate said first and second components being in amounts such that the concentration of the second impurity is smaller than that of the first impurity at the surface of said highly doped surface region.
Claim 5
Dependent Claim
28 words
Semiconductor diffusion source of claim 1, wherein said surface region has one conductivity type and said semiconductor substrate is a silicon semiconductor substrate having an opposite conductivity type.
References Cited (Backward Citations)
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US3365793A
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-04-21 | 1978-10-21 | 1979-04-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-04-21 | 1982-10-21 | 1983-04-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-04-21 | 1986-10-21 | 1987-04-22 | $7700.00 | Window Closed / Lapsed |