Microwave power transistor

Claim 2

A semiconductor device comprising: a semiconductor planar substrate of a first conductivity type; a collector region of the said first conductivity type, said collector region being contiguous to said substrate; a base region of a second conductivity type, said base region being contiguous to said collector region; a plurality of connections to said base region, said connections being arranged in transverse substantially linear rows and columns; a plurality of substantially separate emitter regions of said first conductivity type, said emitter regions being contiguous to said base region, said emitter regions being located substantially at the center of four of the said connections to said base region wherein the said four connections are adjacent one another; and said emitter regions having a substantially diamond shape, the ratio of the length of the junction between each of said emitter regions and said base region at the intersection of said junction with the surface of said semiconductor device to the area of said base region in contact with said collector region divided by the number of said emitter regions being greater than (5/6).(1/w), w being the linear distance between the two most proximate angles along said junction at said surface.

Claim 3

The combination of claim 1 wherein said first conductivity type is N-type material and said second conductivity type is P-type material.

Claim 4

A complex transistor device with four transistor device bodies interconnected therein comprising in combination: four transistor bodies, said bodies being substantially rectangular in shape and said bodies being arranged in a square with the longer sides of each of said bodies being in parallel with the sides of said square and said transistor bodies being separated from one another; means to support said transistor bodies, said means having first and second planar surfaces; a first set of conductive fingers coupled to emitter contacts of said transistor bodies, said first set of conductive fingers being interconnected at the center of said square; a second set of conductive fingers coupled to base contacts of said transistor bodies, said second set of conductive fingers being interconnected at the periphery of said square on said first planar surface of said means to support said transistor bodies, wherein each of said transistor bodies comprises: a semiconductor planar substrate of a first conductivity type; a collector region of the said first conductivity type, said collector region being contiguous to said substrate; a base region of a second conductivity type, said base region being contiguous to said collector region; a plurality of connections to said base region, said connections being arranged in transverse substantially linear rows and columns; a plurality of substantially separate emitter regions of said first conductivity type, said emitter regions being contiguous to said base region, said emitter regions being located substantially at the center of four of the said connections to said base region wherein the said four connections are adjacent one another; and said emitter regions having a substantially diamond shape, the ratio of the length of the junction between each of said emitter regions and said base region aT the intersection of said junction with the surface of said semiconductor device to the area of said base region in contact with said collector region divided by the number of said emitter regions being greater than (5/6).(1/w), w being the linear distance between the two most proximate angles along said junction at said surface.

Claim 5

A complex transistor device with four transistor device bodies interconnected therein comprising in combination: four transistor bodies, said bodies being substantially rectangular in shape and said bodies being arranged in a square with the longer sides of each of said bodies being in parallel with the sides of said square and said transistor bodies being separated from one another; means to support said transistor bodies, said means having first and second planar surfaces; a first set of conductive fingers coupled to emitter contacts of said transistor bodies, said first set of conductive fingers being interconnected at the center of said square; a second set of conductive fingers coupled to base contacts of said transistor bodies, said second set of conductive fingers being interconnected at the periphery of said square on said first planar surface of said means to support said transistor bodies, wherein each of said transistor bodies comprises: a semiconductor planar substrate of a first conductivity type; a collector region of the said first conductivity type, said collector region being contiguous to said substrate; a base region of a second conductivity type, said base region being contiguous to said collector region; a plurality of connections to said base region, said connections being arranged in transverse substantially linear rows and columns; a plurality of substantially separate emitter regions of said first conductivity type, said emitter regions being contiguous to said base region, said emitter regions being located substantially at the center of four of the said connections to said base region wherein the said four connections are adjacent one another; and said emitter regions having a substantially diamond shape, the ratio of the length of the junction between each of said emitter regions and said base region aT the intersection of said junction with the surface of said semiconductor device to the area of said base region in contact with said collector region divided by the number of said emitter regions being greater than (5/6).(1/w), w being the linear distance between the two most proximate angles along said junction at said surface.

Claim 6

The combination of claim 3 further comprising: means for providing one or more connections to said region of semiconductor material of a first conductivity type; and means for providing a connection to each region of said plurality of regions of said first conductivity type.

Claim 7

The combination of claim 4 further comprising: means for interconnecting said plurality of connections to said region of semiconductor material of said second conductivity type; and means for interconnecting each of said connections to each region of said plurality of regions of said first conductivity type.

Claim 8

The combination of claim 3 further comprising means for coupling said transistor device to input signal providing means and output signal utilization means in an amplifying circuit.

Claim 9

The combination of claim 6 further comprising means for supplying bias voltage to said transistor device.

Claim 10

The combination of claim 7 wherein said coupling means comprises impedance matching means for matching input and output impedances of said transistor device to said amplifying circuit.