Facsimile signal transmission apparatus

Claim 2

Facsimile signal transmission apparatus comprising: a generator generating facsimile signals including frame synchronization signals, an A-D converter including a sampling circuit which converts facsimile signals obtained from said facsimile signal generator into a digital series which indicates a prescribed number of picture elements, a means for taking out from said sampling circuit simultaneously as two channel signals first and second series of signals mutually shifted only by a half-length portion of one scanning line from any two lines at least mutually adjacent of scanning line information, and a D-A converter for obtaining an analog base band signal by combining the two channel digital signals obtained from said taking out means.

Claim 3

Apparatus according to claim 1 which further comprises a frame synchronization circuit for synchronizing said frame synchronization signals with the functioning of the facsimile signal transmission apparatus.

Claim 4

Apparatus according to claim 2 wherein said frame synchronization circuit includes a first flip-flop which detects frame synchronizing signals in said facsimile signals and gives out outputs, a first counter which gives out output when outputs from said first flip-flop are continuously counted by a prescribed number of counts and a second counter which sends a carry signal to said take-out means when there is output from said first counter and it is reset and the prescribed number of clock signals have been counted.

Claim 5

Apparatus according to claim 1 wherein said means for taking out two channel signals includes a gate control circuit which, corresponding to the aforementioned frame synchronization signals, sequentially generates a plurality of gate control signals; a first logic gate circuit which is gate controlled by said gate control signals; a memory device which under control of said logic gate circuit sequentially stores one line portion of a scanning line from the output of said sampling circuit; and a second logic gate circuit controlled by said gate control signals, from the information of at least two mutually adjacent scanning lines stored in said memory device, for simultaneously taking out, as two channel signals, two series of signals containing an information quantity each corresponding to one-half portion of a scanning line and mutually shifted by one-half length of one scanning line.

Claim 6

Apparatus according to claim 4 wherein said gate control circuit comprises means to generate first through sixth inclusive gate control signals, the aforementioned first logic gate circuit having first to third OR gates selectively applied said first to sixth gate control signals and first to third AND gates, outputs of said OR gates being applied to input terminal of one side of each thereof, and to the input terminals of the other side the outputs of the D-A converter being applied; the aforementioned memory device being comprised of first to third memories which receive outputs from said first to third AND gates; and the aforementioned second logic gate circuit is comprised of fourth to ninth OR gates to which signals of the aforementioned first to sixth gate controls are selectively applied; fourth to ninth AND gates in which outputs of said OR gates are applied to input terminal of one side, and to input terminals of the other side outputs of the aforementioned first to third memories are applied; and tenth and eleventh OR gates which put out, as signals of the aforementioned two channels, selectively applied outputs of fourth to ninth AND gates.

Claim 7

Apparatus according to claim 4 wherein said gate control circuit is constructed so that it will put out first through 20th gate control signals, said first logic gate circuit includes first to fifth OR gates to which are applied selectively the aforementioned first to 20th gate control signals; first to fifth AND gates to which the output from said OR gate is applied to input terminals of one side, and the output of the D-A converter is applied to input terminals of the other side; the aforementioned memory device is comprised of first to fifth memories receiving outputs of the first to fifth AND gates; the second logic gate circuit is comprised of sixth to tenth OR gates to which signals of the aforementioned first to 20th gates are selectively applied; sixth to 15th AND gates to which outputs of said OR gates are applied to input terminals on one side, and to the input terminal on the other side are applied outputs of aforementioned first to fifth memories; and 11th and 12th OR gates to which are applied in common the outputs of said sixth to 15th AND gates.

Claim 8

Apparatus according to claim 1 wherein said D-A converter is comprised of a first switching circuit to which is applied the aforementioned first channel signal; an exclusive OR gate to the two input terminals to which are applied signals of the two aforementioned first and second channel signals; an inverter which inverts the output of said exclusive OR gate; a transistor switching circuit to which is applied output of said inverter; and a resistor circuit where, according to the conductive condition of the aforementioned first and second switching circuits, the output voltage is determined.

Claim 9

Apparatus according to claim 1 which further comprises a channel separator which receives the aforementioned base band signals and expands the band-width and separates the two channel signal series; a second gate control which, corresponding to the aforementioned frame synchronization signals, generates sequentially a plurality of gate control signals; a first logic gate circuit which is gate controlled by said gate signal; a memory device which under control of said first logic gate circuit sequentially stores scanning lines, one line at a time, from the output of the aforementioned channel separator; a second logic gate circuit controlled by the aforementioned gate control signals in which scanning line information stored in said memory device is read out in prescribed sequence and for compounding a group of digital facsimile signals; a D-A converter for reproducing analog facsimile signals from the aforementioned digital signals; and a facsimile reproduction device, responding to output of said D-A converter and reproducing the picture.

Claim 10

Apparatus according to claim 8 wherein said second gate control circuit is constructed to put out first to 20th gate control signals, the aforementioned first logic gate circuit includes first to 10th OR gates to which are applied selectively aforementioned first to twentieth gate control signals; the first to tenth gates where outputs of said OR gates are applied to input terminals on one side, and to the input terminals on the other side are applied to outputs from the aforementioned channel separator; and 11th to 15th OR gates to which are applied the outputs of said AND gates; the aforementioned memory devices are comprised of first to fifth memories which store outputs from 11th to 15th OR gates; the aforementioned second logic gate circuit is comprised of 16th to 20th OR gates which receive first to 20th gate control signals from the aforementioned fourth logic gate circuit, eleventh to 15th AND gates which pass scanning line information from said first to fifth memories when the gate is opened due to output of said OR gate, and a 21st OR gate to which outputs of said AND gates are commonly supplied.

Claim 11

Apparatus according to claim 8 wherein said channel separator is comprised of a plurality of comparators to which the aforementioned base band signals are applied respectively to one side of the input, and to the other side are applied reference signals; and a further logic gate circuit which combines the outputs of said comparators and generates said signal of two channels.