US3875657A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Dielectrically isolated semiconductor devices
Assignee: Motorola Solutions Inc
•
Filing: 1973-09-04
•
Granted: 1975-04-08
•
Expires: 1993-09-04
Abstract
Abstract A method of fabricating dielectrically isolated integrated circuit devices wherein a highly doped monocrystalline semiconductor wafer of a predetermined conductivity type and a substrate of polycrystalline semiconductor material are separated by an insulating layer of silicon dioxide. A working layer of semiconductor material of the same conductivity type, but of a lower impurity concentration as the monocrystalline semiconductor wafer is expitaxially deposited onto the monocrystalline semiconductor wafer after which a plurality of semiconductor devices are formed in the monocrystalline epitaxial layer. A portion of the working epitaxial layer is chemically etched away to expose a portion of the highly doped monocrystalline semiconductor wafer. Isolation moats between each of the semiconductor devices are formed by a second chemical etching step and conductive connections are formed to active portions of each semiconductor device.
Inventors
- 👤 Ronald N Clarke
- 👤 Richard E Hejmanowski
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 15:15
CPC Classifications
H; H10; H10P; H10P95/00; H10W; H10W10/00; H10W10/01; H10W10/011; H10W10/10; Y; Y10; Y10S; Y10S148/00; Y10S148/051; Y10S148/085; Y10S148/15; Y10S438/00; Y10S438/977
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
186 words
A method for fabricating a semiconductor structure containing a plurality of electrically isolated semiconductor devices which comprises: a. forming a wafer of high conductivity first type semiconductor material; b. epitaxially depositing a first layer of lower conductivity material of first conductivity type on the first surface of said wafer; c. forming a second layer of material on the second surface of said wafer, said second layer of material being non-electrically conductive with respect to separated points of said wafer; d. forming a plurality of semiconductor devices on said epitaxial layer; and e. removing a portion of said first layer whereby the underlying portion of said wafer will be exposed; f. etching a groove along a part of said exposed portion between at least two of said semiconductor devices, said groove extending from first surface of said wafer to said second layer of material whereby said semiconductor devices separated by said groove will be electrically isolated, while leaving at least a part of said exposed portion between said two devices; and g. making an ohmic contact to said remaining part of said exposed portion of said wafer.
Claim 2
Independent Claim
186 words
A method for fabricating a semiconductor structure containing a plurality of electrically isolated semiconductor devices which comprises: a. forming a wafer of high conductivity first type semiconductor material; b. epitaxially depositing a first layer of lower conductivity material of first conductivity type on the first surface of said wafer; c. forming a second layer of material on the second surface of said wafer, said second layer of material being non-electrically conductive with respect to separated points of said wafer; d. forming a plurality of semiconductor devices on said epitaxial layer; and e. removing a portion of said first layer whereby the underlying portion of said wafer will be exposed; f. etching a groove along a part of said exposed portion between at least two of said semiconductor devices, said groove extending from first surface of said wafer to said second layer of material whereby said semiconductor devices separated by said groove will be electrically isolated, while leaving at least a part of said exposed portion between said two devices; and g. making an ohmic contact to said remaining part of said exposed portion of said wafer.
Claim 3
Dependent Claim
19 words
The method of claim 1 where said second layer comprises semiconductor material of opposite conductivity type as said wafer.
Claim 4
Dependent Claim
13 words
The method of claim 1 where said second layer comprises an insulating material.
Claim 5
Dependent Claim
32 words
The method of claim 3 and further including the step of forming a third layer of semiconductor material over said second layer whereby extra mechanical strength will be imparted to said structure.
Claim 6
Dependent Claim
32 words
The method of claim 4 and further including the step of etching said wafer on its second surface prior to forming said second layer whereby the thickness of said wafer is reduced.
Claim 7
Dependent Claim
17 words
The method of claim 5 where said ohmic contact is made prior to etching of said groove.
Claim 8
Dependent Claim
17 words
The method of claim 6 and further including the step of filling said groove with insulating material.
Claim 9
Dependent Claim
11 words
The method of claim 7 where said semiconductor material is silicon.
Claim 10
Dependent Claim
12 words
The method of claim 8 where said second layer is silicon dioxide.
Claim 11
Dependent Claim
32 words
The method of claim 2 and further including the step of etching said wafer on its second surface prior to forming said second layer whereby the thickness of said wafer is reduced.
Claim 12
Dependent Claim
17 words
The method of claim 10 where said ohmic contact is made prior to etching of said groove.
Claim 13
Dependent Claim
17 words
The method of claim 11 and further including the step of filling said groove with insulating material.
Claim 14
Dependent Claim
11 words
The method of claim 12 where said semiconductor material is silicon.
Claim 15
Independent Claim
214 words
A method for fabricating a semiconductor structure containing a plurality of electrically isolated semiconductor devices which comprises the steps of: a. forming a wafer of high first conductivity type silicon; b. epitaxially depositing a first layer of lower conductivity silicon of first conductivity type on the first surface of said wafer; c. etching the second surface of said wafer whereby the thickness of said wafer is reduced; d. depositing a second layer of silicon dioxide on said second surface; e. depositing a third layer of polycrystalline silicon on said second layer; f. forming a plurality of semiconductor devices on said first layer; g. removing said first layer over a portion of the surface of said wafer whereby an underlying portion of said wafer will be exposed; h. interconnecting said semiconductor devices one connection to each of said devices being made to said exposed portions of said wafer; i. etching a groove along a part of said exposed portion between at least two of said semiconductor devices from the first layer side of said structure, said groove extending to said second layer whereby said semiconductor devices separated by said groove will be electrically isolated while leaving at least that part of said exposed portion having said one connection; j. filling said groove with silicon dioxide.
Claim 16
Independent Claim
214 words
A method for fabricating a semiconductor structure containing a plurality of electrically isolated semiconductor devices which comprises the steps of: a. forming a wafer of high first conductivity type silicon; b. epitaxially depositing a first layer of lower conductivity silicon of first conductivity type on the first surface of said wafer; c. etching the second surface of said wafer whereby the thickness of said wafer is reduced; d. depositing a second layer of silicon dioxide on said second surface; e. depositing a third layer of polycrystalline silicon on said second layer; f. forming a plurality of semiconductor devices on said first layer; g. removing said first layer over a portion of the surface of said wafer whereby an underlying portion of said wafer will be exposed; h. interconnecting said semiconductor devices one connection to each of said devices being made to said exposed portions of said wafer; i. etching a groove along a part of said exposed portion between at least two of said semiconductor devices from the first layer side of said structure, said groove extending to said second layer whereby said semiconductor devices separated by said groove will be electrically isolated while leaving at least that part of said exposed portion having said one connection; j. filling said groove with silicon dioxide.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-04-07 | 1978-10-07 | 1979-04-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-04-07 | 1982-10-07 | 1983-04-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-04-07 | 1986-10-07 | 1987-04-08 | $7700.00 | Window Closed / Lapsed |