Patent US3873372A successfully refreshed from Google Patents.
US3873372A
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Method for producing improved transistor devices
Assignee: International Business Machines Corp
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Filing: 1973-07-09
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Granted: 1975-03-25
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Expires: 1993-07-09
Abstract
Abstract The invention is concerned with methods for producing improved semiconductor devices. The invention is advantageously employable in the fabrication of insulated-gate field-effect transistor devices. The problem of accurately aligning the gate electrode over the channel region, lying between the source region and the drain region of a field effect transistor, is particularly addressed and solved. Accurate and precise field protection of all areas of the field-effect transistor surrounding the channel, source and drain regions is simply and effectively accomplished. The proper alignment of the gate electrode is largely accomplished by utilizing essentially the same mask structure to define the gate, source and drain regions. The same mask structure is utilized to define the area that is field protected.
Inventors
- 👤 William S Johnson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 14:10
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/80; H10D84/82; H10D84/83; H10D84/84; H10W; H10W10/00; H10W10/01; H10W10/011; H10W10/012; H10W10/0125; H10W10/10; H10W10/13; Y; Y10; Y10S; Y10S148/00; Y10S148/043; Y10S148/053; Y10S148/085; Y10S148/114
Claims Analysis
Total Claims: 49
Claim 1
Independent Claim
943 words
A METHOD OF FABRICATING A SEMICONDUCTOR DEVICE HAVING FIRST, SECOND AND THIRD SPATIALLY SEPARATED REGIONS OF A FIRST CONDUCTIVITY TYPE SAID REGIONS RESPECTIVELY, LYING ON AND WITHIN A PLANAR SURFACE OF A SEMICONDUCTOR SUBSTRATE OF SECOND CONDUCTIVITY TYPE, SAID FIRST CONDUCTIVITY TYPE BEING OPPOSITE TO SAID SECOND CONDUCTIVITY TYPE, A FOURTH REGION TO SAID SECOND CONDUCTIVITY TYPE, EXTENDING FROM SAID FIRST REGION TO SAID SECOND REGION, AND A FIFTH REGION OF SAID FIRST CONDUCTIVITY TYPE EXTENDING FROM SAID SECOND REGION TO SAID THIRD REGION, SAID METHOD COMPRISING: A. FORMING A FIRST RELATIVELY THIN INSULATING LAYER OF A FIRST MATERIAL ON SAID PLANAR SURFACE OF SAID SEMICONDUCTOR SUBSTRATE, B. FORMING A SECOND RELATIVELY THIN INSULATING LAYER OF A SECOND MATERIAL ON SAID FIRST INSULATING LAYER, C. FORMING A THIRD RELATIVELY THICK INSULATING LAYER OF A THIRD MATERIAL ON SAID SECOND INSULATING LAYER, D. REMOVING FIRST, SECOND AND THIRD SPATIALLY SEPARATED PORTIONS OF SAID THIRD INSULATING LAYER TO EXPOSE FIRST, SECOND AND THIRD AREAS OF SAID SECOND INSULATING LAYER, E. BOMBARDING THE SURFACE OF SAID SUBSTRATE WITH IMPURITY IONS OF SAID FIRST CONDUCTIVITY TYPE AT AN ENERGY SUFFICIENT TO PENETRATE THROUGH SAID FIRST AND SECOND INSULATING LAYERS AND INSUFFICIENT TO PENETRATE THROUGH SAID FIRST, SECOND AND THIRD INSULATING LAYERS, WHEREBY SAID FIRST, SECOND AND THIRD SPATIALLY SEPARATED REGIONS OF SAID FIRST CONDUCTIVITY TYPE ARE FORMED ON AND WITHIN SAID PLANAR SURFACE OF SAID SEMICONDUCTOR SUBSTRATE, F. FORMING A FOURTH RELATIVELY THICK INSULATING LAYER OF A FOURTH MATERIAL OVER THE SURFACE OF SAID DEVICE, G. REMOVING ALL OF SAID FOURTH INSULATING LAYER EXCEPT FOR TWO DISCRETE PORTIONS THEREOF, RESPECTIVELY COVERING A FIRST PREDETERMINED PRECISELY LOCATED AREA ON THE SURFACE OF SAID DEVICE AND A SECOND PREDETERMINED PRECISELY LOCATED AREA ON THE SURFACE OF SAID DEVICE, SAID FIRST PORTION WHOLLY COVERING PORTIONS OF SAID FIRST, SECOND AND THIRD INSULATING LAYERS WHERE SAID FIRST, SECOND AND THIRD INSULATING LAYERS OVERLAY AN AREA OF SAID PLANAR SURFACE OF SAID SEMICONDUCTOR SUBSTRATE EXTENDING FROM SAID FIRST REGION TO SAID REGION, SAID SECOND PORTION WHOLLY COVERING PORTIONS OF SAID FIRST, SECOND AND THIRD INSULATING LAYERS, WHERE SAID FIRST, SECOND AND THIRD INSULATING LAYERS OVERLY AN AREA OF SAID PLANAR SURFACE OF SAID SEMICONDUCTOR SUBSTRATE EXTENDING FROM SAID SECOND REGION TO SAID THIRD REGION H. REMOVING SAID THIRD INSULATING LAYER EXCEPT FOR THE PORTIONS UNDERLYING SAID FIRST AND SECOND PORTIONS OF SAID FOURTH INSULATING MATERIAL, I. REMOVING SAID PORTIONS OF SAID FOURTH INSULATING MATERIAL J. BOMBARDING THE SURFACE OF SAID SUBSTRATE WITH IMPURITY IONS OF SAID SECOND CONDUCTIVITY TYPE AT AN ENERGY STUFFICIENT TO PENETRATE THE PLANAR SURFACE OF SAID SEMICONDUCTOR IN THE AREA COVERED SOLELY BY SAID FIRST AND SECOND INSULATING LAYERS EHEREBY SAID FIRST AND SECOND PREDETERMINED PRECISELY LOCATED AREAS OF SAID PLANAR SURFACE OF SAID SEMICONDUCTOR SUBSTRATE COVERED BY SAID FIRST, SECOND AND THIRD LAYERS OF INSULATING MATERIAL ARE NOT SUBJECTED TO BOMBARDMENT BY IMPURITY IONS OF SAID SECOND CONDUCTIVITY TYPE, K. REMOVING SAID SECOND INSULATING LAYER FROM THE PLANAR SURFACE AREA OF SAID DEVICE ONLY WHERE THE PLANAR SURFACE OF SAID DEVICE IS SOLELY COVERED BY SAID FIRST AND SECOND INSULATING LAYERS, L. REMOVING SAID FIRST INSULATING LAYER FROM THE PLANAR FACE OF SAID DEVICE ONLY WHERE THE PLANAR SURFACE OF SAID DEVICE IS SOLELY COVERED BY SAID FIRST INSULATING LAYER, M. REMOVING SAID THIRD LAYER OF INSULATING MATERIAL FROM THE PLANAR SURFACE OF SAID DEVICE WHERE SAID PLANAR SURFACE OF SAID DEVICE IS SOLELY COVERED BY SAID FIRST, SECOND AND THIRD INSULATING LAYERS, N. FORMING A FIRST RELATIVELY THICK INSULATING COATING ON THE ENTIRE AREA OF SAID PLANAR SURFACE OF SAID SEMICONDUCTOR DEVICE EXCEPT FOR SAID FIRST AND SECOND PREDERTIMINED PRECISELY LOCATED AREAS ON THE PLANAR SURFACE OF SAID SEMICONDUCTOR DEVICE, O. REMOVING SAID SECOND INSULATING LAYER FORM SAID FIRST AND SECOND PREDETERMINED PRECISELY LOCATED AREAS ON THE PLANAR SURFACE OF SAID SEMICONDUCTOR DEVICE, P. REMOVING SAID FIRST INSULATING LAYER FROM SAID FIRST AND SECOND PREDETERMINED PRECISELY LOCATED AREAS ON THE PLANAR SURFACE OF SAID SEMICONDUCTOR DIVICE, Q. FORMING A SECOND RELATIVELY THIN COATING OF INSULATING MATERIAL OVER THE ENTIRE PLANAR SURFACE AREA OF THE DEVICE, R. BOMBARDING THE ENTIRE PLANAR SURFACE OF SAID DEVICE WITH IMPURITY IONS OF SAID SECOND CONDUCTIVITY TYPE AT AN ENERGY SUFFICIENT ONLY TO FORM SAID FOURTH REGION OF SAID SECOND CONDUCTIVITY TYPE LYING ON AND WITHIN SAID PLANAR SURFACE OF SAID SEMICONDUCOR SUBSTRATE AND A SIXTH REGION OF SAID SECOND CONDUCTIVITY TYPE LYING ON AND WITHIN SAID PLANAR SURFACE OF SAID SEMICONDUCTOR SUBSTRATE, SAID FOURTH AND SAID SIXTH REGIONS OF SAID SECOND CONDUCTIVITY TYPE RESPECTIVELY CORRESPONDING IDENTICALLY IN AREA AND LOCATION ON SAID PLANAR SURFACE TO SAID FIRST AND SECOND PREDETERMINED PRECISELY LOCATED AREAS ON SAID PLANAR SURFACE OF SAID SEMICONDUCTOR DEVICE, S. FORMING A RELATIVELY THICK FIFTH LAYER OF INSULATING MATERIAL OVER THE PLANAR SURFACE OF SAID DEVICE, T. OPENING A WINDOW AREA IN SAID FIFTH INSULATING AREA SAID WINDOW AT LEAST FULLY ENCOMPASSING SAID SECOND PREDETERMINED PRECISELY LOCATED AREA ON SAID PLANAR SURFACE OF SAID SEMICONDUCTOR DEVICE, U. BOMBARDING THE ENTIRE PLANAR SURFACE OF SAID DEVICE WITH IMPURITY IONS OF SAID FIRST CONDUCTIVITY TYPE AT AN ENERGY SUFFICIENT ONLY TO CAUSE SAID SIXTH REGION OF SAID SECOND CONDUCTIVITY TYPE TO BECOME SAID FIFTH REGION OF SAID FIRST CONDUCTIVITY TYPE, SAID FITH REGIONCORRESPONDING IDENTICALLY IN AREA AND LOCATION TO SAID SECOND PREDETERMINED PRECISELY LOCATED AREA ON SAID PLANAR SURFACE OF SAID SEMICONDUCTOR SUBSTRATE, V. REMOVING SAID FIFTH LAYER OF INSULATING MATERIAL, W. CUTTING A PLURALITY OF DISCRETE SPATIALLY DISPLACED CONTACT OPENINGS IN SAID FIRST RELATIVELY THICK INSULATING COATING TO EXPOSE SAID PLANAR SURFACE OF SAID SEMICONDUCTOR SUBSTRATE ATSAID OPENINGS, X. FORMING APLURALITY OF DISCRETE ELECTRICAL CONTACTS ON THE RESULTANT DEVICE.
Claim 2
Independent Claim
943 words
A METHOD OF FABRICATING A SEMICONDUCTOR DEVICE HAVING FIRST, SECOND AND THIRD SPATIALLY SEPARATED REGIONS OF A FIRST CONDUCTIVITY TYPE SAID REGIONS RESPECTIVELY, LYING ON AND WITHIN A PLANAR SURFACE OF A SEMICONDUCTOR SUBSTRATE OF SECOND CONDUCTIVITY TYPE, SAID FIRST CONDUCTIVITY TYPE BEING OPPOSITE TO SAID SECOND CONDUCTIVITY TYPE, A FOURTH REGION TO SAID SECOND CONDUCTIVITY TYPE, EXTENDING FROM SAID FIRST REGION TO SAID SECOND REGION, AND A FIFTH REGION OF SAID FIRST CONDUCTIVITY TYPE EXTENDING FROM SAID SECOND REGION TO SAID THIRD REGION, SAID METHOD COMPRISING: A. FORMING A FIRST RELATIVELY THIN INSULATING LAYER OF A FIRST MATERIAL ON SAID PLANAR SURFACE OF SAID SEMICONDUCTOR SUBSTRATE, B. FORMING A SECOND RELATIVELY THIN INSULATING LAYER OF A SECOND MATERIAL ON SAID FIRST INSULATING LAYER, C. FORMING A THIRD RELATIVELY THICK INSULATING LAYER OF A THIRD MATERIAL ON SAID SECOND INSULATING LAYER, D. REMOVING FIRST, SECOND AND THIRD SPATIALLY SEPARATED PORTIONS OF SAID THIRD INSULATING LAYER TO EXPOSE FIRST, SECOND AND THIRD AREAS OF SAID SECOND INSULATING LAYER, E. BOMBARDING THE SURFACE OF SAID SUBSTRATE WITH IMPURITY IONS OF SAID FIRST CONDUCTIVITY TYPE AT AN ENERGY SUFFICIENT TO PENETRATE THROUGH SAID FIRST AND SECOND INSULATING LAYERS AND INSUFFICIENT TO PENETRATE THROUGH SAID FIRST, SECOND AND THIRD INSULATING LAYERS, WHEREBY SAID FIRST, SECOND AND THIRD SPATIALLY SEPARATED REGIONS OF SAID FIRST CONDUCTIVITY TYPE ARE FORMED ON AND WITHIN SAID PLANAR SURFACE OF SAID SEMICONDUCTOR SUBSTRATE, F. FORMING A FOURTH RELATIVELY THICK INSULATING LAYER OF A FOURTH MATERIAL OVER THE SURFACE OF SAID DEVICE, G. REMOVING ALL OF SAID FOURTH INSULATING LAYER EXCEPT FOR TWO DISCRETE PORTIONS THEREOF, RESPECTIVELY COVERING A FIRST PREDETERMINED PRECISELY LOCATED AREA ON THE SURFACE OF SAID DEVICE AND A SECOND PREDETERMINED PRECISELY LOCATED AREA ON THE SURFACE OF SAID DEVICE, SAID FIRST PORTION WHOLLY COVERING PORTIONS OF SAID FIRST, SECOND AND THIRD INSULATING LAYERS WHERE SAID FIRST, SECOND AND THIRD INSULATING LAYERS OVERLAY AN AREA OF SAID PLANAR SURFACE OF SAID SEMICONDUCTOR SUBSTRATE EXTENDING FROM SAID FIRST REGION TO SAID REGION, SAID SECOND PORTION WHOLLY COVERING PORTIONS OF SAID FIRST, SECOND AND THIRD INSULATING LAYERS, WHERE SAID FIRST, SECOND AND THIRD INSULATING LAYERS OVERLY AN AREA OF SAID PLANAR SURFACE OF SAID SEMICONDUCTOR SUBSTRATE EXTENDING FROM SAID SECOND REGION TO SAID THIRD REGION H. REMOVING SAID THIRD INSULATING LAYER EXCEPT FOR THE PORTIONS UNDERLYING SAID FIRST AND SECOND PORTIONS OF SAID FOURTH INSULATING MATERIAL, I. REMOVING SAID PORTIONS OF SAID FOURTH INSULATING MATERIAL J. BOMBARDING THE SURFACE OF SAID SUBSTRATE WITH IMPURITY IONS OF SAID SECOND CONDUCTIVITY TYPE AT AN ENERGY STUFFICIENT TO PENETRATE THE PLANAR SURFACE OF SAID SEMICONDUCTOR IN THE AREA COVERED SOLELY BY SAID FIRST AND SECOND INSULATING LAYERS EHEREBY SAID FIRST AND SECOND PREDETERMINED PRECISELY LOCATED AREAS OF SAID PLANAR SURFACE OF SAID SEMICONDUCTOR SUBSTRATE COVERED BY SAID FIRST, SECOND AND THIRD LAYERS OF INSULATING MATERIAL ARE NOT SUBJECTED TO BOMBARDMENT BY IMPURITY IONS OF SAID SECOND CONDUCTIVITY TYPE, K. REMOVING SAID SECOND INSULATING LAYER FROM THE PLANAR SURFACE AREA OF SAID DEVICE ONLY WHERE THE PLANAR SURFACE OF SAID DEVICE IS SOLELY COVERED BY SAID FIRST AND SECOND INSULATING LAYERS, L. REMOVING SAID FIRST INSULATING LAYER FROM THE PLANAR FACE OF SAID DEVICE ONLY WHERE THE PLANAR SURFACE OF SAID DEVICE IS SOLELY COVERED BY SAID FIRST INSULATING LAYER, M. REMOVING SAID THIRD LAYER OF INSULATING MATERIAL FROM THE PLANAR SURFACE OF SAID DEVICE WHERE SAID PLANAR SURFACE OF SAID DEVICE IS SOLELY COVERED BY SAID FIRST, SECOND AND THIRD INSULATING LAYERS, N. FORMING A FIRST RELATIVELY THICK INSULATING COATING ON THE ENTIRE AREA OF SAID PLANAR SURFACE OF SAID SEMICONDUCTOR DEVICE EXCEPT FOR SAID FIRST AND SECOND PREDERTIMINED PRECISELY LOCATED AREAS ON THE PLANAR SURFACE OF SAID SEMICONDUCTOR DEVICE, O. REMOVING SAID SECOND INSULATING LAYER FORM SAID FIRST AND SECOND PREDETERMINED PRECISELY LOCATED AREAS ON THE PLANAR SURFACE OF SAID SEMICONDUCTOR DEVICE, P. REMOVING SAID FIRST INSULATING LAYER FROM SAID FIRST AND SECOND PREDETERMINED PRECISELY LOCATED AREAS ON THE PLANAR SURFACE OF SAID SEMICONDUCTOR DIVICE, Q. FORMING A SECOND RELATIVELY THIN COATING OF INSULATING MATERIAL OVER THE ENTIRE PLANAR SURFACE AREA OF THE DEVICE, R. BOMBARDING THE ENTIRE PLANAR SURFACE OF SAID DEVICE WITH IMPURITY IONS OF SAID SECOND CONDUCTIVITY TYPE AT AN ENERGY SUFFICIENT ONLY TO FORM SAID FOURTH REGION OF SAID SECOND CONDUCTIVITY TYPE LYING ON AND WITHIN SAID PLANAR SURFACE OF SAID SEMICONDUCOR SUBSTRATE AND A SIXTH REGION OF SAID SECOND CONDUCTIVITY TYPE LYING ON AND WITHIN SAID PLANAR SURFACE OF SAID SEMICONDUCTOR SUBSTRATE, SAID FOURTH AND SAID SIXTH REGIONS OF SAID SECOND CONDUCTIVITY TYPE RESPECTIVELY CORRESPONDING IDENTICALLY IN AREA AND LOCATION ON SAID PLANAR SURFACE TO SAID FIRST AND SECOND PREDETERMINED PRECISELY LOCATED AREAS ON SAID PLANAR SURFACE OF SAID SEMICONDUCTOR DEVICE, S. FORMING A RELATIVELY THICK FIFTH LAYER OF INSULATING MATERIAL OVER THE PLANAR SURFACE OF SAID DEVICE, T. OPENING A WINDOW AREA IN SAID FIFTH INSULATING AREA SAID WINDOW AT LEAST FULLY ENCOMPASSING SAID SECOND PREDETERMINED PRECISELY LOCATED AREA ON SAID PLANAR SURFACE OF SAID SEMICONDUCTOR DEVICE, U. BOMBARDING THE ENTIRE PLANAR SURFACE OF SAID DEVICE WITH IMPURITY IONS OF SAID FIRST CONDUCTIVITY TYPE AT AN ENERGY SUFFICIENT ONLY TO CAUSE SAID SIXTH REGION OF SAID SECOND CONDUCTIVITY TYPE TO BECOME SAID FIFTH REGION OF SAID FIRST CONDUCTIVITY TYPE, SAID FITH REGIONCORRESPONDING IDENTICALLY IN AREA AND LOCATION TO SAID SECOND PREDETERMINED PRECISELY LOCATED AREA ON SAID PLANAR SURFACE OF SAID SEMICONDUCTOR SUBSTRATE, V. REMOVING SAID FIFTH LAYER OF INSULATING MATERIAL, W. CUTTING A PLURALITY OF DISCRETE SPATIALLY DISPLACED CONTACT OPENINGS IN SAID FIRST RELATIVELY THICK INSULATING COATING TO EXPOSE SAID PLANAR SURFACE OF SAID SEMICONDUCTOR SUBSTRATE ATSAID OPENINGS, X. FORMING APLURALITY OF DISCRETE ELECTRICAL CONTACTS ON THE RESULTANT DEVICE.
Claim 3
Dependent Claim
161 words
The method of claim 1 wherein said first relatively thin insulating layer is silicon dioxide, said second relatively thin insulating layer is silicon nitride, said third relatively thick insulating layer is silicon dioxide, said fourth Relatively thick insulating layer is photoresist material, said first relatively thick insulating coating is silicon dioxide, said second relatively thin insulating coating is silicon dioxide, said relatively thick fifth insulating layer is photoresist, said first region of first conductivity type is the source of a first field effect transistor, said fourth region of second conductivity type is the channel of said first field effect transistor, said second region of said first conductivity type is the drain of said first field effect transistor and the source of a second field effect transistor, said fifth region of said first conductivity type is the channel of said second field effect transistor, and said third region of said first conductivity type is the drain of said second field effect transistor.
Claim 4
Dependent Claim
121 words
The method of claim 2 wherein said semiconductor substrate is 1-0-0 oriented silicon, of 14 to 18 ohm cm. P type, said first relatively thin layer of silicon dioxide is approximately 500A in thickness and is dry thermally grown at approximately 970*C, said second relatively thin layer of silicon nitride is approximately 400A in thickness and is chemically vapor deposited at 800*C, said third relatively thick layer of silicon dioxide is approximately 10,000A in thickness and is chemically vapor deposited at 800*C, said first relatively thick coating of silicon dioxide is approximately 6,500A in thickness and is wet grown at approximately 900*C, said second relatively thin coating of silicon dioxide is approximately 500A in thickness and dry grown at approximately 970*C.
Claim 5
Dependent Claim
182 words
The method of claim 3 wherein said two discrete portions of photoresist material respectively overlay a first predetermined precisely located area on the surface of said device and a second predetermined precisely located area on the surface of said device, said first portion wholly covering portions of said first, second and third insulating layer where said first, second and third insulating layers overlay an area of said planar surface of said semiconductor substrate extending from said first region to second region, said second portion wholly covering portions of said first, second and third insulating layers, where said first, second and third insulating layers, overlay an area of said planar surface of said semiconductor substrate extending from said second region to said third region, where said two discrete portions of photoresist and said layers underlaying said portions are common masking structures respectively and with modification utilized to precisely define the locations of the channels of said first and second field effect transistors, the accurate positioning of gate electrodes over said channels and the planar area of said semiconductor device that is field protected.
Claim 6
Dependent Claim
221 words
In a method for fabricating a semiconductor device having a semiconductor substrate of a first conductivity type, said substrate having at least one planar surface on which adjacently spaced first, second and third regions of a second conductivity type have been formed, a first layer of relatively thin insulating material has been formed on a first precisely defined area of said planar surface extending from said first region to said second region, a second layer of relatively thin insulating material has been formed on second precisely defined area of said planar surface extending from said second region to said third region wherein the improved method comprises the steps A. forming a relatively thick third layer of insulating material over said entire planar surface except said first and second areas, B. providing a fourth region of said first conductivity type in said planar surface beneath said first area, C. providing a fifth region of said second conductivity type beneath said second area, D. providing three electrical contacts respectively to sAid first, second and third regions of said planar surface, E. providing two electrical contacts, respectively overlaying said first and second relatively thin layers of insulating material on said first and second precisely defined area of said planar surface, whereby fourth and fifth regions are respectively capacitively coupled to said two electrical contacts.
Claim 7
Dependent Claim
221 words
In a method for fabricating a semiconductor device having a semiconductor substrate of a first conductivity type, said substrate having at least one planar surface on which adjacently spaced first, second and third regions of a second conductivity type have been formed, a first layer of relatively thin insulating material has been formed on a first precisely defined area of said planar surface extending from said first region to said second region, a second layer of relatively thin insulating material has been formed on second precisely defined area of said planar surface extending from said second region to said third region wherein the improved method comprises the steps A. forming a relatively thick third layer of insulating material over said entire planar surface except said first and second areas, B. providing a fourth region of said first conductivity type in said planar surface beneath said first area, C. providing a fifth region of said second conductivity type beneath said second area, D. providing three electrical contacts respectively to sAid first, second and third regions of said planar surface, E. providing two electrical contacts, respectively overlaying said first and second relatively thin layers of insulating material on said first and second precisely defined area of said planar surface, whereby fourth and fifth regions are respectively capacitively coupled to said two electrical contacts.
Claim 8
Dependent Claim
75 words
In a method for fabricating a semiconductor device as recited in claim 5 wherein said first and second layers of relatively thin insulating material each consist of a relatively thin layer of silicon dioxide formed on said planar surface and a relatively thin layer of silicon nitride formed on said thin layer of silicon dioxide, and said relatively thick third layer of insulating material is silicon dioxide of approximately 6,500 to 10,000 A in thickness.
Claim 9
Dependent Claim
99 words
In a method for fabricating a semiconductor device as recited in claim 6 wherein subsequent to step (a) of claim 6 and prior to step (b) of claim 6 the following steps are performed: a-1. said relatively thin layers of silicon nitride are removed, a-2. said relatively thin layers of silicon dioxide are removed, and a-3. a relatively thin layer of silicon dioxide is formed over the entire planar surface of the device whereby said first and second precisely defined areas of said planar surface are respectively overlayed with a layer of silicon dioxide of approximately 500A in thickness.
Claim 10
Dependent Claim
50 words
In a method of fabricating a semiconductor device as recited in claim 6 wherein said relatively thin silicon nitride layer is approximately 400A in thickness, said relatively thin silicon dioxide layer is approximately 500 A in thickness and said relatively thick layer of silicon dioxide is approximately 6,500A in thickness.
Claim 11
Independent Claim
533 words
A method of fabricating a semiconductor device having first, second and third spatially separated regions of a first conductivity type, respectively lying on and within a planar surface of a semiconductor substrate of second conductivity type, said first conductivity type being opposite to said second conductivity type, a fourth region of said second conductivity type extending from said first region to said second region, and a fifth region of said first conductivity type extending from said second region to said third region, said method comprising: A. forming a first insulating layer of a first material on said planar surface of said semiconductor substrate, B. forming a second insulating layer of a second material of said first insulating layer, C. selectively removing portions of said first and second insulating layers to expose first, second and third discrete portions of said planar surface of said semiconductor substrate, said first exposed surface being spaced adjacent to said second exposed surface and said second exposed surface being spaced adjacent to said third exposed surface, D. introducing impurities of said first conductivity type into said semiconductor substrate via said first, second and third exposed portions of said planar surface of said semiconductor substrate, whereby said first, second and third spatially separated regions of said first conductivity type are formed, E. forming first and second segments of insulating material, said first segment of insulating material overlaying portions of said first and second insulating layers in a first precisely located area of said planar surface extending from said first region to said second region, and said second segment of insulating material overlaying portions of said first and second insulating layers in a second precisely located area of said planar surface extending from said second region to said third region, F. introducing impurities of said second conductivity type into the entire planar surface of said semiconductor substrate except said first and second precisely located areas of said planar surface, which respectivelY underlay said first and second segments of insulating material, G. removing said entire first and second layers of insulating material except the portions of said first and second insulating layers underlying said first and second segments of insulating material, H. removing said first and second segments of insulating material whereby said entire planar surface of said semiconductor substrate is exposed except said first and second precisely located areas which respectively underlay said portions of said first and second insulating layers, I. forming a relatively thick coating of insulating material over substantially the entire planar surface of said semiconductor substrate, where substantially the entire planar surface of said semiconductor substrate is defined as the entire planar surface of said semiconductor substrate except for said first and second precisely located areas, J. introducing impurities of said second conductivity type into a region of said planar surface of said semiconductor substrate bounded by said first precisely located area, whereby said fourth region of said second conductivity is provided, K. introducing impurities of said first conductivity type into a region of said planar surface of said semiconductor substrate bounded by said second precisely located area, whereby said fifth region of said first conductivity type is provided, and L. providing the device with electrical contacts.
Claim 12
Independent Claim
533 words
A method of fabricating a semiconductor device having first, second and third spatially separated regions of a first conductivity type, respectively lying on and within a planar surface of a semiconductor substrate of second conductivity type, said first conductivity type being opposite to said second conductivity type, a fourth region of said second conductivity type extending from said first region to said second region, and a fifth region of said first conductivity type extending from said second region to said third region, said method comprising: A. forming a first insulating layer of a first material on said planar surface of said semiconductor substrate, B. forming a second insulating layer of a second material of said first insulating layer, C. selectively removing portions of said first and second insulating layers to expose first, second and third discrete portions of said planar surface of said semiconductor substrate, said first exposed surface being spaced adjacent to said second exposed surface and said second exposed surface being spaced adjacent to said third exposed surface, D. introducing impurities of said first conductivity type into said semiconductor substrate via said first, second and third exposed portions of said planar surface of said semiconductor substrate, whereby said first, second and third spatially separated regions of said first conductivity type are formed, E. forming first and second segments of insulating material, said first segment of insulating material overlaying portions of said first and second insulating layers in a first precisely located area of said planar surface extending from said first region to said second region, and said second segment of insulating material overlaying portions of said first and second insulating layers in a second precisely located area of said planar surface extending from said second region to said third region, F. introducing impurities of said second conductivity type into the entire planar surface of said semiconductor substrate except said first and second precisely located areas of said planar surface, which respectivelY underlay said first and second segments of insulating material, G. removing said entire first and second layers of insulating material except the portions of said first and second insulating layers underlying said first and second segments of insulating material, H. removing said first and second segments of insulating material whereby said entire planar surface of said semiconductor substrate is exposed except said first and second precisely located areas which respectively underlay said portions of said first and second insulating layers, I. forming a relatively thick coating of insulating material over substantially the entire planar surface of said semiconductor substrate, where substantially the entire planar surface of said semiconductor substrate is defined as the entire planar surface of said semiconductor substrate except for said first and second precisely located areas, J. introducing impurities of said second conductivity type into a region of said planar surface of said semiconductor substrate bounded by said first precisely located area, whereby said fourth region of said second conductivity is provided, K. introducing impurities of said first conductivity type into a region of said planar surface of said semiconductor substrate bounded by said second precisely located area, whereby said fifth region of said first conductivity type is provided, and L. providing the device with electrical contacts.
Claim 13
Dependent Claim
448 words
In a method for fabricating a semiconductor device including a semiconductor substrate with a planar surface having first, second, third, fourth and fifth regions lying on and within said planar surface of said semiconductor substrate, said substrate and said second region being of a first conductivity type and said first, third, fourth and fifth being of a second conductivity type, the steps comprising: A. forming a first insulating mask layer of material on said planar surface of said semiconductor substrate; B. forming a second insulating mask layer over said first insulating mask layer; C. opening first, second and third discrete windows in said first and second mask layers to expose first, second and third discrete areas on said planar surface; D. introducing impurities of a second conductivity type into said semiconductor substrate in regions underlying said first, second and third areas, whereby said first, third and fifth regions of said second conductivity type are formed; E. removing said second insulating mask layer except for first and second portions of said second insulating mask layer, said first portion of said second insulating mask overlaying a first precisely defined area where said first insulating mask extends from said first region to said third region of second conductivity type, and said second portion of said second insulating mask overlaying a second precisely defined area where said first insulating mask extends from said third region to said fifth region of said second conductivity type; F. introducing impurities of said first type into the entire planar surface area of said semiconductor substrate other than said first and second precisely defined areas; G. removing the entire exposed area of said first insulating mask layer of material; H. removing said first and second portions of said second insulating mask layer, whereby except for said first and second precisely defined areas, said entire planar surface of said semiconductor substrate is exposed; I. forming a relatively thick third layer of insulating material overlaying said entire planar surface except said first and second precisely defined areas of said planar surface; J. introducing impurities of said first conductivity type into said first precisely defined area of said planar surface to provide said second region of said first conductivity type; K. introducing impurities of said second conductivity type into said second precisely defined area of said pLanar surface to provide said fourth region of said second conductivity type; L. fabricating electrical contacts for the device upon said relatively thick third layer of insulating material, certain of said electrical contacts making direct electrical contact with said first, third and fifth regions of said device, others of said electrical contacts being capacitively coupled to said second and fourth regions of said device.
Claim 14
Dependent Claim
448 words
In a method for fabricating a semiconductor device including a semiconductor substrate with a planar surface having first, second, third, fourth and fifth regions lying on and within said planar surface of said semiconductor substrate, said substrate and said second region being of a first conductivity type and said first, third, fourth and fifth being of a second conductivity type, the steps comprising: A. forming a first insulating mask layer of material on said planar surface of said semiconductor substrate; B. forming a second insulating mask layer over said first insulating mask layer; C. opening first, second and third discrete windows in said first and second mask layers to expose first, second and third discrete areas on said planar surface; D. introducing impurities of a second conductivity type into said semiconductor substrate in regions underlying said first, second and third areas, whereby said first, third and fifth regions of said second conductivity type are formed; E. removing said second insulating mask layer except for first and second portions of said second insulating mask layer, said first portion of said second insulating mask overlaying a first precisely defined area where said first insulating mask extends from said first region to said third region of second conductivity type, and said second portion of said second insulating mask overlaying a second precisely defined area where said first insulating mask extends from said third region to said fifth region of said second conductivity type; F. introducing impurities of said first type into the entire planar surface area of said semiconductor substrate other than said first and second precisely defined areas; G. removing the entire exposed area of said first insulating mask layer of material; H. removing said first and second portions of said second insulating mask layer, whereby except for said first and second precisely defined areas, said entire planar surface of said semiconductor substrate is exposed; I. forming a relatively thick third layer of insulating material overlaying said entire planar surface except said first and second precisely defined areas of said planar surface; J. introducing impurities of said first conductivity type into said first precisely defined area of said planar surface to provide said second region of said first conductivity type; K. introducing impurities of said second conductivity type into said second precisely defined area of said pLanar surface to provide said fourth region of said second conductivity type; L. fabricating electrical contacts for the device upon said relatively thick third layer of insulating material, certain of said electrical contacts making direct electrical contact with said first, third and fifth regions of said device, others of said electrical contacts being capacitively coupled to said second and fourth regions of said device.
Claim 15
Dependent Claim
79 words
In a method for fabricating a semiconductor device as recited in claim 10 wherein: said first insulating mask layer comprises a layer of silicon nitride approximately 400 A in thickness superimposed upon a layer of silicon dioxide approximately 500 A in thickness; said first and second portions of said second insulating mask layer are respectively silicon dioxide approximately 10,000 A in thickness; and said relatively thick third layer of insulating material is silicon dioxide approximately 6,500 A in thickness.
Claim 16
Dependent Claim
98 words
In a method for fabricating a semiconductor device as recited in claim 11, wherein subsequent to step (i) and prior to step (j) the following steps are performed: i-1. said 400 A thick layer of silicon nitride is removed, i-2. said 500 A thick layer of silicon dioxide is removed, and i-3. a fresh relatively thin layer of silicon dioxide is formed over the entire planar surface of the device whereby said first and second precisely defined areas of said planar surface are respectively overlayed solely with a layer of silicon dioxide of approximatley 500 A in thickness.
Claim 17
Dependent Claim
102 words
In a method for fabricating a semiconductor device as claimed in claim 12 wherein: in step (d) said impurities of said second conductivity type are introduced by arsenic capsule diffusion; in step (f) said impurities of said first type are introduced by implanting boron ions, 2 X 1013 boron ions/cm2 at 110 keV; in step (j) said impurities of said first conductivity type are introduced by implanting boron ions, 7.9 X 1011 boron ions/cm2 at 30 keV; and in step (k) said impurities of said second conductivity type are introduced by implanting phosphorous ions 2.4 X 1012 phosphorous ions/cm2 at 95 keV.
Claim 18
Dependent Claim
38 words
In a method for fabricating a semiconductor device as recited in claim 13 where, in step (f), the implantation of boron ions provides field protection of field effect transistors fabricated in accordance with the method of claim 13.
Claim 19
Dependent Claim
131 words
In a method for fabricating a semiconductor device as recited in claim 12 further characterized by: in step (c) said first, second and third discrete windows are formed only in said second mask layer; in step (d) said impurities of said second conductivity type are introduced by implanting phosphorous ions, 5 X 1015 phosphorous ions/cm2 at 150 keV; in step (f) said impurities of said first conductivity type are introduced by implanting boron ions 2 X 1013 boron ions/cm2 at 110 keV; in step (j) said impurities of said first conductivity type are introduced by implanting boron ions, 7.9 X 1011 boron ions/cm2 at 30 keV: and in step (k) said impurities of said second conductivity type are introduced by implanting phosphorous ions, 2.4 X 1012 phosphorous ions/cm2 at 95 keV.
Claim 20
Dependent Claim
348 words
In a method for fabricating a semiconductor device on a semiconductor substrate of a first conductivity type having at least one planar surface, said method including the following steps: A. forming a first layer of oxidation resistant material over the entire planar surface of said semiconductor substrate; B. forming a second layer of material on said entire first layer with the exception of at least first and second adjacently spaced regions of said first layer; C. subjecting said first and second regions of said first layer to Ion implantatiOn by Ions of said second conductivity type, whereby first and second regions of a second conductivity type are formed on and beneath said planar surface of said semiconductor substrate and beneath said first and second adjacently spaced regions of said first layer of oxidation resistant material; D. removing said second layer of material; E. forming a third layer of material in a third region on said first layer, said third region extending from said first region to said second region of said first layer, said third region of said third layer overlaying a third region on said planar surface extending from said first region of second conductivity type to said second region of second conductivity type; F. subjecting said first layer, except for the third region thereof underlying said third layer to ion bombardment by ions of said first conductivity type whereby except for said third region on said planar surface of said semiconductor substrate, the entire planar surface of said semiconductor substrate has been subjected to Ion implantation by Ions of said first conductivity type; G. removing said first layer except for the remaining portion of said first layer underlying said third layer; H. removing said third layer; I. thermally oxidizing the planar surface of said semiconductor substrate with the exception of the remaining portion said first layer which overlies said third region of said planar surface of said semiconductor substrate, whereby an insulating layer is formed over the entire exposed area of said planar surface of said semiconductor substrate; K. and providing electrical contacts to said device.
Claim 21
Dependent Claim
348 words
In a method for fabricating a semiconductor device on a semiconductor substrate of a first conductivity type having at least one planar surface, said method including the following steps: A. forming a first layer of oxidation resistant material over the entire planar surface of said semiconductor substrate; B. forming a second layer of material on said entire first layer with the exception of at least first and second adjacently spaced regions of said first layer; C. subjecting said first and second regions of said first layer to Ion implantatiOn by Ions of said second conductivity type, whereby first and second regions of a second conductivity type are formed on and beneath said planar surface of said semiconductor substrate and beneath said first and second adjacently spaced regions of said first layer of oxidation resistant material; D. removing said second layer of material; E. forming a third layer of material in a third region on said first layer, said third region extending from said first region to said second region of said first layer, said third region of said third layer overlaying a third region on said planar surface extending from said first region of second conductivity type to said second region of second conductivity type; F. subjecting said first layer, except for the third region thereof underlying said third layer to ion bombardment by ions of said first conductivity type whereby except for said third region on said planar surface of said semiconductor substrate, the entire planar surface of said semiconductor substrate has been subjected to Ion implantation by Ions of said first conductivity type; G. removing said first layer except for the remaining portion of said first layer underlying said third layer; H. removing said third layer; I. thermally oxidizing the planar surface of said semiconductor substrate with the exception of the remaining portion said first layer which overlies said third region of said planar surface of said semiconductor substrate, whereby an insulating layer is formed over the entire exposed area of said planar surface of said semiconductor substrate; K. and providing electrical contacts to said device.
Claim 22
Dependent Claim
13 words
In the method of claim 16 wherein said first layer is silicon nitride.
Claim 23
Dependent Claim
13 words
In the method of claim 16 wherein said first layer is aluminum oxide.
Claim 24
Dependent Claim
13 words
In the method of claim 16 wherein said second layer is silicon dioxide.
Claim 25
Dependent Claim
13 words
In the method of claim 16 wherein said second layer is photo resist.
Claim 26
Dependent Claim
12 words
In the method of claim 16 wherein said second layer is aluminum.
Claim 27
Dependent Claim
24 words
In the method of claim 16 wherein said first layer is comprised of a layer of silicon nitride on a layer of silicon dioxide.
Claim 28
Dependent Claim
13 words
In the method of claim 16 wherein said third layer is silicon dioxide.
Claim 29
Dependent Claim
13 words
In the method of claim 16 wherein said third layer is photo resist.
Claim 30
Dependent Claim
17 words
In the method of claim 16 wherein the sequence of performing steps F and G is reversed.
Claim 31
Dependent Claim
25 words
In the method of claim 16 wherein said second layer is comprised of a layer of photo resist on a thin layer of silicon dioxide.
Claim 32
Dependent Claim
16 words
In the method of claim 26 wherein only the photo resist is removed in step D.
Claim 33
Dependent Claim
31 words
In the method of claim 16 wherein subsequent to step I and prior to step K said portion of said first layer is removed and a fresh insulating layer is formed.
Claim 34
Dependent Claim
38 words
In the method of claim 16 wherein said third region on said planar surface of said semiconductor substrate is subjected to Ion implantation by Ions of either said first or said second conductivity type prior to step K.
Claim 35
Dependent Claim
344 words
In a method for fabricating a semiconductor device on a semiconductor substrate of a first conductivity type having at least one planar surface, said method including the following steps: A. forming a first layer of oxidation resistant material over the entire planar surface of said semiconductor substrate; B. forming a second layer of material on said entire first layer with the exception of at least first and second adjacently spaced regions of said first layer; C. removing at least said first and second regions of said first layer whereby first and second regions of said planar surface of said semiconductor substrate are exposed; D. diffusing an impurity of a second conductivity type into at least said first and second regions of said planar surface of said semiconductor substrate, whereby first and second regions of said second conductivity type are formed on and beneath said planar surface of said semiconductoR substrate; E. removing said second layer of material; F. forming a third layer of material in a third region of said first layer, said third region extending from said first region on said planar surface of said semiconductor substrate to said second region on said planar surface of said semiconductor substrate; G. subjecting said planar surface of said semiconductor substrate with the exception of the third region thereof which underlies said third layer of Ion bombardment by Ions of said first conductivity type whereby except for said third region on said planar surface of said semiconductor substrate has been subjected to Ion implantation by Ions of said first conductivity type; H. removing said first layer except for the remaining portion of said first layer underlying said third layer; I. removing said third layer; J. thermally oxidizing the planar surface of said semiconductor substrate with the exception of said remaining portion of said first layer which overlies said third region of said planar surface of said semiconductor substrate, whereby an insulating layer is formed over the entire exposed surface area of said planar surface of said semiconductor substrate; K. and providing electrical contacts to said device.
Claim 36
Dependent Claim
344 words
In a method for fabricating a semiconductor device on a semiconductor substrate of a first conductivity type having at least one planar surface, said method including the following steps: A. forming a first layer of oxidation resistant material over the entire planar surface of said semiconductor substrate; B. forming a second layer of material on said entire first layer with the exception of at least first and second adjacently spaced regions of said first layer; C. removing at least said first and second regions of said first layer whereby first and second regions of said planar surface of said semiconductor substrate are exposed; D. diffusing an impurity of a second conductivity type into at least said first and second regions of said planar surface of said semiconductor substrate, whereby first and second regions of said second conductivity type are formed on and beneath said planar surface of said semiconductoR substrate; E. removing said second layer of material; F. forming a third layer of material in a third region of said first layer, said third region extending from said first region on said planar surface of said semiconductor substrate to said second region on said planar surface of said semiconductor substrate; G. subjecting said planar surface of said semiconductor substrate with the exception of the third region thereof which underlies said third layer of Ion bombardment by Ions of said first conductivity type whereby except for said third region on said planar surface of said semiconductor substrate has been subjected to Ion implantation by Ions of said first conductivity type; H. removing said first layer except for the remaining portion of said first layer underlying said third layer; I. removing said third layer; J. thermally oxidizing the planar surface of said semiconductor substrate with the exception of said remaining portion of said first layer which overlies said third region of said planar surface of said semiconductor substrate, whereby an insulating layer is formed over the entire exposed surface area of said planar surface of said semiconductor substrate; K. and providing electrical contacts to said device.
Claim 37
Dependent Claim
13 words
In the method of claim 30 wherein said first layer is silicon nitride.
Claim 38
Dependent Claim
13 words
In the method of claim 30 wherein said first layer is aluminum oxide.
Claim 39
Dependent Claim
13 words
In the method of claim 30 wherein said second layer is silicon dioxide.
Claim 40
Dependent Claim
13 words
In the method of claim 30 wherein said second layer is photo resist.
Claim 41
Dependent Claim
12 words
In the method of claim 30 wherein said second layer is aluminum.
Claim 42
Dependent Claim
24 words
In the method of claim 30 wherein said first layer is comprised of a layer of silicon nitride on a layer of silicon dioxide.
Claim 43
Dependent Claim
13 words
In the method of claim 30 wherein said third layer is silicon dioxide.
Claim 44
Dependent Claim
13 words
In the method of claim 30 wherein said third layer is photo resist.
Claim 45
Dependent Claim
18 words
In the method of claim 30 wherein the order of execution of steps F and G is reversed.
Claim 46
Dependent Claim
25 words
In the method of claim 30 wherein said second layer is comprised of a layer of photo resist on a thin layer of silicon dioxide.
Claim 47
Dependent Claim
15 words
In the method of claim 40 wherein only the photoresist is removed in step D.
Claim 48
Dependent Claim
31 words
In the method of claim 30 wherein subsequent to step I and prior to step K said portion of said first layer is removed and a fresh insulating layer is formed.
Claim 49
Dependent Claim
38 words
In the method of claim 30 wherein said third region on said planar surface of said semiconductor substrate is subjected to Ion implantation by Ions of either said first or said second conductivity type prior to step K.
References Cited (Backward Citations)
US3479237A
Cited
US3596347A
Cited
US3653978A
Cited
US3717507A
Cited
US3747203A
Cited
US3634738A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-03-24 | 1978-09-23 | 1979-03-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-03-24 | 1982-09-23 | 1983-03-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-03-24 | 1986-09-23 | 1987-03-25 | $7700.00 | Window Closed / Lapsed |