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US3872452A
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Floating addressing system and method
Assignee: International Business Machines Corp
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Filing: 1974-04-17
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Granted: 1975-03-18
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Expires: 1994-04-17
Abstract
Abstract Floating addressing system and method wherein addressable units, such as storage cards, with different numbers of addresses constituting integral multiples of a basic number (e.g., 4k, 8k, 12k) are plugged into a back panel in random sequence. All cards with the same numbers of addresses are identical. Means associated with these cards enable them to recognize different addresses depending upon where they are plugged in, irrespective of their particular numbers of addresses or plug-in sequence. Thus, any card, irrespective of its address size, may be plugged in to replace one with a different address size, and all cards will automatically be adjusted to recognize their respective new addresses without requiring substitution of different decode logic cards, rewiring or recabling.
Inventors
- 👤 Edward H Stoops
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 15:19
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/06; G06F12/0646; G06F12/0669; G06F12/0676
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
292 words
Floating addressing system, comprising a plurality of addressable units having different numbers of addresses constituting integral multiples of a predetermined basic number, each of said units having a similar preselected number of pins representing floating address inputs and an identical number of pins representing floating address outputs, each set of input and output pins being arranged in low to high order sequence, means for applying a preselected coded signal to the input pins of a first one of said units, means connecting each input pin in each unit with that particular one of the output pins on the same unit that is indicative of the number of addresses suCh unit has, each of said particular output pins being displaced a similar predetermined number of places toward the high order position indicative of the number of said multiples of said basic number of addresses in said same unit to cause the coded input signal to be shifted toward the high order position said predetermined number of places and provide end around carries to generate any low order positions, means connecting the output pins of each unit always with the same corresponding associated input pins in the succeeding unit, encoding means for each unit for encoding the floating address input to that particular unit to provide for such unit an encoded output assigned address indicative of the number of multiples of said basic number of addresses that precedes that particular unit, comparator means associated with each unit for comparing the encoded assigned address with a selectable address corresponding to that of the unit to be selected to provide an output signal when the selectable address equals the encoded assigned address, and means for conveying the selectable address in parallel to each such comparator means.
Claim 2
Dependent Claim
292 words
Floating addressing system, comprising a plurality of addressable units having different numbers of addresses constituting integral multiples of a predetermined basic number, each of said units having a similar preselected number of pins representing floating address inputs and an identical number of pins representing floating address outputs, each set of input and output pins being arranged in low to high order sequence, means for applying a preselected coded signal to the input pins of a first one of said units, means connecting each input pin in each unit with that particular one of the output pins on the same unit that is indicative of the number of addresses suCh unit has, each of said particular output pins being displaced a similar predetermined number of places toward the high order position indicative of the number of said multiples of said basic number of addresses in said same unit to cause the coded input signal to be shifted toward the high order position said predetermined number of places and provide end around carries to generate any low order positions, means connecting the output pins of each unit always with the same corresponding associated input pins in the succeeding unit, encoding means for each unit for encoding the floating address input to that particular unit to provide for such unit an encoded output assigned address indicative of the number of multiples of said basic number of addresses that precedes that particular unit, comparator means associated with each unit for comparing the encoded assigned address with a selectable address corresponding to that of the unit to be selected to provide an output signal when the selectable address equals the encoded assigned address, and means for conveying the selectable address in parallel to each such comparator means.
Claim 3
Dependent Claim
41 words
The system according to claim 1, wherein said means for applying the preselected coded signal applies said signal as a continuous d.c. signal, thereby to cause said encoded output address to be continuously present as an input to the comparator means.
Claim 4
Dependent Claim
31 words
The system according to claim 1, wherein all of said units having the same numbers of addresses are of identical configuration irrespective of which unit they are sequentially in the system.
Claim 5
Dependent Claim
87 words
The system according to claim 1, including means providing to each of said units a base address distinctive to that particular unit, and wherein the first-mentioned means includes means providing a distinctive delta floating address input to the input pins of said first one of said units, and the encoding means for each unit includes an encoder for encoding the delta floating address input, and an adder for adding such encoded delta input to the base address to provide said encoded output assigned address for such unit.
Claim 6
Dependent Claim
74 words
The system according to claim 1, wherein the respective input pins on each unit are connected electrically straight across to the same order output pins on such unit when the latter has said basic number of addresses and are connected to the output pins with a shift toward the high order position a number of places equal to one less than the number of integral multiples of said basic number present in such unit.
Claim 7
Dependent Claim
49 words
The system according to claim 1, wherein the respective input pins on each unit are connected to the associated output pins with a shift toward the high order position that number of places equal to the number of integral multiples of said basic number of addresses in such unit.
Claim 8
Dependent Claim
176 words
In a floating addressing system, the combination of a plurality of addressable units having different numbers of addresses constituting integral multiples of a predetermined basic number, each of said units having a similar preselected number of pins representing floating address inputs and floating address outputs arranged in sets in low to high order sequence, means for applying a preselected coded signal to the input pins of a first one of said units, means connecting the set of input pins in each unit with that particular set of the output pins on the same unit that is indicative of the number of addresses such unit has, means connecting each set of output pins of each unit with the same corresponding associated set of input pins in the succeeding unit, and control circuit means for each unit providing for such unit an output assigned address indicative of the number of multiples of said basic number of addresses that precedes that particular unit, said control circuit means including means responsive to the floating address input to that particular unit.
Claim 9
Dependent Claim
176 words
In a floating addressing system, the combination of a plurality of addressable units having different numbers of addresses constituting integral multiples of a predetermined basic number, each of said units having a similar preselected number of pins representing floating address inputs and floating address outputs arranged in sets in low to high order sequence, means for applying a preselected coded signal to the input pins of a first one of said units, means connecting the set of input pins in each unit with that particular set of the output pins on the same unit that is indicative of the number of addresses such unit has, means connecting each set of output pins of each unit with the same corresponding associated set of input pins in the succeeding unit, and control circuit means for each unit providing for such unit an output assigned address indicative of the number of multiples of said basic number of addresses that precedes that particular unit, said control circuit means including means responsive to the floating address input to that particular unit.
Claim 10
Dependent Claim
34 words
In the system according to claim 7, wherein said means for applying the preselected coded signal applies said signal as a continuous d.c. signal, thereby to cause said output address to be continuously present.
Claim 11
Dependent Claim
83 words
In the system according to claim 7, said first-mentioned means comprising means providing a distinctive delta floating address input to the input pins of said first one of said units, and said control circuit means further including means providing to each of said units a base address distinctive to that particular unit, an encoder for encoding the delta floating address input, and an adder for adding such encoded delta input to the base address to provide said output assigned address for such unit.
Claim 12
Dependent Claim
59 words
In the system according to claim 9, comparator means associated with each unit for comparing the output assigned address with a selectable address corresponding to that of the unit to be selected to provide an output signal when the selectable address equals the assigned address, and means for conveying the selectable address in parallel to each such comparator means.
Claim 13
Dependent Claim
84 words
In the system according to claim 7, the respective input pins on each unit being connected electrically straight across to the same order output pins on such unit when the latter has said basic number of addresses and connected to the output pins with a shift toward the high order position a number of places equal to one less than the number of integral multiples of said basic number present in such unit when said unit has more than said basic number of addresses.
Claim 14
Dependent Claim
50 words
In the system according to claim 7, the respective input pins on each unit are connected to the associated output pins with a shift toward the high order position that number of places equal to the number of integral multiples of said basic number of addresses present in such unit.
Claim 15
Dependent Claim
28 words
In the system according to claim 7, the output pins of each unit being converted electrically straight across with the same order input pins of the succeeding unit.
References Cited (Backward Citations)
US3736574A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-03-17 | 1978-09-16 | 1979-03-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-03-17 | 1982-09-16 | 1983-03-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-03-17 | 1986-09-16 | 1987-03-18 | $7700.00 | Window Closed / Lapsed |