Patent US3870962A successfully refreshed from Google Patents.
US3870962A
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Means to control pulse width and repetition rate of binary counter means
Assignee: Solitron Devices Inc
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Filing: 1973-04-25
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Granted: 1975-03-11
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Expires: 1993-04-25
Abstract
Abstract A CMOS circuit including a first gate, a shift register, a second gate, an electronic switch and a latch circuit operatively related therein such that pulse width and the repetition rate thereof from the shift register to the second gate is equated, respectively, to a period of input signals to the shift register and the frequency of the input signal to the first gate, said circuit also including electronic means to provide clock signals and counter means signals, respectively being the input signals aforesaid, said circuit being adaptable to employ a third gate operatively related to said latch to set same in accordance with said counter means signals and another input signal means.
Inventors
- 👤 Errico John J D
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 20:17
CPC Classifications
G; G04; G04G; G04G99/00
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
204 words
A means to control pulse width and repetition rate comprising: a shift register having first and second clock signal inputs and a pulse signal input and two outputs a latch means connected to one of said two (outputs of said shift register such that a signal from said one of said two outputs of said shift register will reset said latch means, said latch means also having means to receive a signal to set said latch means; a first gAte means connected to said latch means to receive an output signal of said latch means, said first gate means comparing said output signal of said latch means with another frequency signal for generating a pulse signal, said first gate means being connected to said shift register to deliver said pulse signal to said pulse signal input of said shift register; and a second gate means having multiple inputs at least one of which receives one of said first and second clock signals and another of which receives said one of said two outputs of said shift register connected to said latch means whereby a pulse of precise width and of a controlled repitition rate is provided at the output of said second gate means.
Claim 2
Dependent Claim
204 words
A means to control pulse width and repetition rate comprising: a shift register having first and second clock signal inputs and a pulse signal input and two outputs a latch means connected to one of said two (outputs of said shift register such that a signal from said one of said two outputs of said shift register will reset said latch means, said latch means also having means to receive a signal to set said latch means; a first gAte means connected to said latch means to receive an output signal of said latch means, said first gate means comparing said output signal of said latch means with another frequency signal for generating a pulse signal, said first gate means being connected to said shift register to deliver said pulse signal to said pulse signal input of said shift register; and a second gate means having multiple inputs at least one of which receives one of said first and second clock signals and another of which receives said one of said two outputs of said shift register connected to said latch means whereby a pulse of precise width and of a controlled repitition rate is provided at the output of said second gate means.
Claim 3
Dependent Claim
204 words
A means to control pulse width and repetition rate comprising: a shift register having first and second clock signal inputs and a pulse signal input and two outputs a latch means connected to one of said two (outputs of said shift register such that a signal from said one of said two outputs of said shift register will reset said latch means, said latch means also having means to receive a signal to set said latch means; a first gAte means connected to said latch means to receive an output signal of said latch means, said first gate means comparing said output signal of said latch means with another frequency signal for generating a pulse signal, said first gate means being connected to said shift register to deliver said pulse signal to said pulse signal input of said shift register; and a second gate means having multiple inputs at least one of which receives one of said first and second clock signals and another of which receives said one of said two outputs of said shift register connected to said latch means whereby a pulse of precise width and of a controlled repitition rate is provided at the output of said second gate means.
Claim 4
Dependent Claim
204 words
A means to control pulse width and repetition rate comprising: a shift register having first and second clock signal inputs and a pulse signal input and two outputs a latch means connected to one of said two (outputs of said shift register such that a signal from said one of said two outputs of said shift register will reset said latch means, said latch means also having means to receive a signal to set said latch means; a first gAte means connected to said latch means to receive an output signal of said latch means, said first gate means comparing said output signal of said latch means with another frequency signal for generating a pulse signal, said first gate means being connected to said shift register to deliver said pulse signal to said pulse signal input of said shift register; and a second gate means having multiple inputs at least one of which receives one of said first and second clock signals and another of which receives said one of said two outputs of said shift register connected to said latch means whereby a pulse of precise width and of a controlled repitition rate is provided at the output of said second gate means.
Claim 5
Dependent Claim
27 words
The structure of claim 1 wherein said shift register receives both a CL and a CL signal and said second gate means receives only the CL signal.
Claim 6
Dependent Claim
14 words
The structure of claim 1 wherein the first and second gates are NAND gates.
Claim 7
Dependent Claim
21 words
The structure of claim 1 wherein the first gate is a NAND gate and the second gate is a NOR gate.
Claim 8
Dependent Claim
28 words
The structure of claim 4 wherein a third gate is connected between a power source signal and a frequency signal to deliver a set signal to said latch.
Claim 9
Dependent Claim
13 words
The structure of claim 5 wherein said third gate is a NOR gate.
Claim 10
Dependent Claim
25 words
The structure of claim 1 wherein an electronic switch is connected between said second gate a power source and an output terminal for said circuit.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-03-10 | 1978-09-09 | 1979-03-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-03-10 | 1982-09-09 | 1983-03-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-03-10 | 1986-09-09 | 1987-03-11 | $7700.00 | Window Closed / Lapsed |