MOSFET circuitry for integrated chips interfacing with higher voltage devices

Claim 1

In an integrated circuit chip of the MOSFET variety having an output terminal to be controlled as to effective voltage potential, and to which is applied a biasing voltage having value relative to ground in excess of the MOSFET breakdown voltage the improvement of: an output circuit in the MOSFET chip as connected between said terminal and ground in the chip, and having a first FET-transistor having its gate controlled from internal circuitry in the chip between conduction and non-conduction, the output circuit further having a second FET-transistor having its gate controlled by a particular voltage for being permanently biased to conduction, and serially connected to the first transistor, the common drain-to-source junction of the first and second transistors being isolated from any other non-ground external bias for maintaining the second FET non-conducting except upon drop to ground or near ground potential of the potential at said junction, so that the potential of the drain of the second MOSFET is not being applied to any other MOSFET in the chip under conditions of conduction of the second FET transistor; and said serially connected first and second transistors being connected between ground and said terminal, so that said excess biasing voltage is applied to the drain of the second FET and for non-conductive first transistor the effective voltage across its main electrodes is composed of said biasing voltage as reduced by the gate voltage as applied to the gate of said second transistor.