Patent US3866064A successfully refreshed from Google Patents.
US3866064A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Cmos analog switch
Assignee: Harris Corp
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Filing: 1973-08-22
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Granted: 1975-02-11
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Expires: 1993-08-22
Abstract
Abstract A complementary metal oxide semiconductor switch interconnected such that body voltages of both the P channel and N channel MOS devices are limited to one forward diode drop of their source and drain voltages, and results in a uniform threshold voltage and low uniform switch ''''on'''' resistance.
Inventors
- 👤 Charles Roy Gregory
- 👤 William Harold White
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 18:09
CPC Classifications
H; H03; H03K; H03K17/00; H03K17/51; H03K17/56; H03K17/687; H03K17/6871; H03K17/6872; H03K2217/00; H03K2217/0018
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
158 words
A CMOS switch having an input terminal and an output terminal, comprising: a P channel metal oxide semiconductor device having a body, a source, a drain and a gate; a complementary N channel metal oxide semiconductor device having a body, a source, a drain and a gate, said devices connected in parallel between the input terminal and output terminal of said switch through the respective source-drain paths of said devices, to be rendered simultaneously conductive and simultaneously non-conductive upon application of appropriate gating signals to the respective gates of said devices and thereupon permit the passage and block the passage, respectively, of signals between said input and output terMinals; and means coupled to the bodies oof said devices for connecting said bodies of said devices to a common point of electrical potential when said switch is rendered conductive and disconnecting said bodies of said devices from said common point of electrical potential when said switch is rendered non-conductive.
Claim 2
Dependent Claim
158 words
A CMOS switch having an input terminal and an output terminal, comprising: a P channel metal oxide semiconductor device having a body, a source, a drain and a gate; a complementary N channel metal oxide semiconductor device having a body, a source, a drain and a gate, said devices connected in parallel between the input terminal and output terminal of said switch through the respective source-drain paths of said devices, to be rendered simultaneously conductive and simultaneously non-conductive upon application of appropriate gating signals to the respective gates of said devices and thereupon permit the passage and block the passage, respectively, of signals between said input and output terMinals; and means coupled to the bodies oof said devices for connecting said bodies of said devices to a common point of electrical potential when said switch is rendered conductive and disconnecting said bodies of said devices from said common point of electrical potential when said switch is rendered non-conductive.
Claim 3
Dependent Claim
39 words
A CMOS switch as in claim 1 including a diode between said source and said body of each said devices whereby said body is limited to one forward diode drop of said source when said switch is rendered conductive.
Claim 4
Dependent Claim
21 words
A CMOS switch as in claim 2 including a diode between said drain and said body of each of said devices.
Claim 5
Dependent Claim
32 words
A CMOS switch as in claim 3 wherein said means includes a first switching means controlled by said gating signal for providing a conduction path between said bodies of said complementary devices.
Claim 6
Dependent Claim
33 words
A CMOS switch as in claim 3 wherein said means includes second switching means controlled by said gating signals for back biasing said bodies of said complementary devices with respect to their sources.
Claim 7
Dependent Claim
85 words
A CMOS switch having an input terminal and an output terminal comprising: a pair of complementary metal oxide semiconductor devices dielectrically isolated having gates and bodies and being connected in parallel between said input and output terminals by their sources and drains; and a first means connected to said pair''s bodies for providing a conduction path between said bodies in response to appropriate gating signals applied to said first means and for limiting the maximum voltage between said source and said bodies of said pair.
Claim 8
Dependent Claim
85 words
A CMOS switch having an input terminal and an output terminal comprising: a pair of complementary metal oxide semiconductor devices dielectrically isolated having gates and bodies and being connected in parallel between said input and output terminals by their sources and drains; and a first means connected to said pair''s bodies for providing a conduction path between said bodies in response to appropriate gating signals applied to said first means and for limiting the maximum voltage between said source and said bodies of said pair.
Claim 9
Dependent Claim
31 words
A CMOS switch as in claim 6 wherein said maximum voltage is limited to a forward diode drop of a body to source diode inherent in a metal oxide semiconductor device.
Claim 10
Dependent Claim
39 words
A CMOS switch as in claim 7 including a second means connected to said pair''s bodies for back biasing said pair''s bodies with respect to said pair''s sources in response to appropriate nongating signals applied to said pair''s gates.
Claim 11
Dependent Claim
29 words
A CMOS switch as in claim 8 wherein said first means includes two N channel MOS devices having their sources and drains connected in series between said pair''s bodies.
Claim 12
Dependent Claim
67 words
A CMOS switch as in claim 9 wherein said second means includes a p channel MOS device having its source and drain connected between a positive voltage source and said body of said pair''s P channel MOS device; and two N channel MOS devices having their sources and drains connected in series between a negative voltage source and said body of said pair''s N channel MOS device.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-02-10 | 1978-08-12 | 1979-02-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-02-10 | 1982-08-12 | 1983-02-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-02-10 | 1986-08-12 | 1987-02-11 | $7700.00 | Window Closed / Lapsed |