Patent US3863330A successfully refreshed from Google Patents.
US3863330A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Self-aligned double-diffused MOS devices
Assignee: Motorola Solutions Inc
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Filing: 1973-08-02
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Granted: 1975-02-04
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Expires: 1993-08-02
Abstract
Abstract A self-aligning masking technique for making double-diffused MOS devices. First and second openings are formed in a first masking layer, and a thin second oxide layer is formed therein. A silicon nitride layer is formed on the first and second masking layers, a third opening defining the source region is formed in the silicon nitride layer adjacent to the first opening, and the exposed first oxide layer is removed. A first region is diffused through the third opening and extends under the thin second oxide layer, and a second, shallower, opposite conductivity region is diffused through the third opening, the channel region being the region between the boundaries of the first and second diffused regions. The thin second masking layer and the overlying silicon nitride layer form a gate insulator for the MOS device, which gate insulator is automatically aligned to the first and second diffused regions.
Inventors
- 👤 Albert V Kraybill
- 👤 William Rapshys
- 👤 Francis R Yester
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 06:07
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/64; H10D30/65; H10D64/00; H10D64/60; H10D64/66; H10D64/68; H10D64/681; H10D64/685; H10D64/693; H10P; H10P95/00; H10D64/20; H10D64/27; H10D64/311; H10D64/411; H10D64/511; H10D64/514; H10D64/516
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
266 words
A method of making a double-diffused MOSFET semiconductor device comprising the steps of: forming a first insulating layer on a first surface of a substrate of semiconductor; forming a first opening in said first insulator exposing said substrate; forming a second insulating layer on said first insulating layer and on said exposed substrate; forming a second opening in said second insulating layer, exposing said first insulating layer; removing said exposed first insulating layer, exposing said first surface; forming a first region in said substrate through said second opening, said first region being of a first conductivity type, and extending a first predetermined distance under said second insulating layer in said first layer; forming a third opening in said first and second insulating layers, exposing said substrate; forming second and third regions of a second conductivity type in said substrate at said first surface, said second region being formed in said first region through said second opening and extending a second predetermined distance under said second insulating layer, said first region being driven in further to extend a third predetermined distance under said second insulating layer, said second predetermined distance being less than said third predetermiend distance, and said third region being formed external to said first region through said third opening; and forming a conductive gate electrode on said second insulating layer over said first opening, said second predetermined distance being selected to minimize the capacitance between said conductive gate electrode and said second region while providing reliable operation of said double-diffused MOSFET devices, said third predetermined distance being selected to provide an optimized channel length.
Claim 2
Independent Claim
266 words
A method of making a double-diffused MOSFET semiconductor device comprising the steps of: forming a first insulating layer on a first surface of a substrate of semiconductor; forming a first opening in said first insulator exposing said substrate; forming a second insulating layer on said first insulating layer and on said exposed substrate; forming a second opening in said second insulating layer, exposing said first insulating layer; removing said exposed first insulating layer, exposing said first surface; forming a first region in said substrate through said second opening, said first region being of a first conductivity type, and extending a first predetermined distance under said second insulating layer in said first layer; forming a third opening in said first and second insulating layers, exposing said substrate; forming second and third regions of a second conductivity type in said substrate at said first surface, said second region being formed in said first region through said second opening and extending a second predetermined distance under said second insulating layer, said first region being driven in further to extend a third predetermined distance under said second insulating layer, said second predetermined distance being less than said third predetermiend distance, and said third region being formed external to said first region through said third opening; and forming a conductive gate electrode on said second insulating layer over said first opening, said second predetermined distance being selected to minimize the capacitance between said conductive gate electrode and said second region while providing reliable operation of said double-diffused MOSFET devices, said third predetermined distance being selected to provide an optimized channel length.
Claim 3
Dependent Claim
21 words
The method as recited in claim 1 wherein said first insulator is silicon dioxide and said second insulator is silicon nitride.
Claim 4
Dependent Claim
52 words
The method as recited in claim 2 further including the step of forming thermally grown silicon dioxide layers on said exposed substrate in said first opening after forming said first opening and before forming said second insulating layer, said thermally grown silicon dioxide layer being substantially thinner than said first insulating layer.
Claim 5
Dependent Claim
62 words
The method as recited in claim 2 wherein said substrate includes a layer of a second conductivity type on a body of semiconductor, of said first conductivity type, said first surface being on said layer of said second conductivity type, and said first region extends through said layer to said body of semiconduCtor after the forming of said second and third regions.
Claim 6
Dependent Claim
35 words
The method as recited in claim 2 wherein said silicon nitride insulator is subjected to a controlled etching process to remove a nitride lip after forming said first region and before forming said third opening.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-02-03 | 1978-08-05 | 1979-02-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-02-03 | 1982-08-05 | 1983-02-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-02-03 | 1986-08-05 | 1987-02-04 | $7700.00 | Window Closed / Lapsed |