Detector for repetitive digital codes

Claim 2

A detector for detecting the presence of an incoming repetitive code having N bits of digital information, said detector comprising: signal delay means for providing said N bits of said incoming code with a first and a second time delay; majority vote means responsive to said incoming code, said first time delayed code and said second time delayed code for providing bits comprising a majority vote signal related to the nature of the majority of the corresponding bits in said incoming code, said first time delayed code and said second time delayed code; a run-length counter means comprising a counter and an N bit shift register responsive to the bits in said majority vote signal for advancing a count in said counter for one condition related to the majority vote bits and for resetting the count for another condition related to the majority vote bits and for providing said majority vote signal with an N bit delay; and means responsive to a specified count in said counter and to the N bits in said N bit shift register for providing an identification signal corresponding to the particular incoming code.

Claim 3

The detector according to claim 1 wherein said first time delay is an integer multiple of the time interval occupied by the N bits of said incoming code and wherein said seconD time delay is another multiple of the time interval occupied by the N bits of said incoming code.

Claim 4

The detector according to claim 2 wherein said signal delay means comprises first and second serially connected shift registers wherein each of said registers accommodater M N bits, where M is a positive integer greater than one.

Claim 5

The detector according to claim 2 wherein said majority vote means comprises: first, second and third AND gates each having two input terminals and an output terminal, said first AND gate being responsive to said undelayed version of said code and the version of said code from said first shift register, said second AND gate being responsive to said undelayed version of said code and the version of said code from said second shift register, said third AND gate being responsive to the versions of said code from the first and second shift registers; and an OR gate having three input terminals and an output terminal, said three OR gate input terminals being respectively connected to the output terminals of said first, second and third AND gates, the signal provided at the output terminal of said OR gate being said majority vote signal.

Claim 6

The detector according to claim 4 wherein said run-length counter means further comprises an exclusive OR gate for comparing the majority vote signal with the delayed majority vote signal provided by said N bit shift register.

Claim 7

The detector according to claim 5 wherein said count responsive means comprises a read only memory, said memory being addressed from said N bit shift register in response to said specified count in said counter means.

Claim 8

A detector for detecting the presence of an incoming repetitive code, said code comprising N bits of digital information, said detector comprising; first delay means for providing the bits in said incoming repetitive code with a first and a second time delay; means for providing an undelayed version of said repetitive code; comparison means for comparing corresponding bits in any two of: (a) the undelayed code; (b) the first time delayed code; and (c) the second time delayed code and for providing a bit resulting from all comparisons made corresponding to the majority vote between (a), (b) and (c) related to the nature of the particular bits being compared; storage and delay means for storing said majority vote bits and for providing said majority vote bits with a certain time delay; means including a counter, responsive to the undelayed majority vote bits and to the corresponding delayed majority vote bits for incrementing said counter when a particular undelayed and corresponding delayed majority vote bit are the same; and means responsive to a specified count in said counter and to the majority vote bits stored in said storage and delay means for decoding said incoming repetitive code.

Claim 9

A detector for detecting the presence of an incoming repetitive code, said code comprising N bits of digital information, said detector comprising; first delay means for providing the bits in said incoming repetitive code with a first and a second time delay; means for providing an undelayed version of said repetitive code; comparison means for comparing corresponding bits in any two of: (a) the undelayed code; (b) the first time delayed code; and (c) the second time delayed code and for providing a bit resulting from all comparisons made corresponding to the majority vote between (a), (b) and (c) related to the nature of the particular bits being compared; storage and delay means for storing said majority vote bits and for providing said majority vote bits with a certain time delay; means including a counter, responsive to the undelayed majority vote bits and to the corresponding delayed majority vote bits for incrementing said counter when a particular undelayed and corresponding delayed majority vote bit are the same; and means responsive to a specified count in said counter and to the majority vote bits stored in said storage and delay means for decoding said incoming repetitive code.

Claim 10

The detector according to claim 7 wherein said first delay means comprises first and second serially connected shift registers and wherein each of said registers accommodates M N bits, where M is a positive integer greater than one.

Claim 11

The detector according to claim 8 wherein said comparison means comprises: first, second and third AND gates each having two input terminals and an output terminal, said first AND gate being responsive to said underlayed version of said code and the version of said code from said first shift register, said second AND gate being responsive to said underlayed version of said code and the version of said code from said second shift register, said third AND gate being responsive to the versions of said code from the first and second shift registers; and an OR gate having three input terminals and an output terminal, said three OR gate input terminals being respectively connected to the output terminals of said first, second and third AND gates, the signal provided at the output terminal of said OR gates being said majoritY signal.

Claim 12

The detector according to claim 9 wherein said storage and delay means comprises an N bit shift register.

Claim 13

The detector according to claim 10 wherein said count responsive means comprises a read only memory, said memory being addressed from said N bit shift register in response to said specified count.

Claim 14

A detector for detecting the presence of an incoming repetitive code, said code comprising N bits of digital information, said detector comprising: first signal delay means for providing said N bits of said incoming code with a first time delay; second signal delay means for providing said N bits of said incoming code with a second time delay; means for providing an underlayed version of said incoming code; first means for compraing the corresponding bits in said repetitive code between any tow of: (a) said undelayed version of said code; (b) the version of said code having said first time delay; and (c) the version of said code having said second time delay, said comparing means providing first, second and third intermediate signals, respectively resulting from the comparisons of any two of (a), (b) and (c), said first comparing means further comprising means responsive to said first, second and third intermediate signals for providing a majority signal corresponding to the majority vote as to the nature of the bits in (a), (b) and (c); signal storage and delay means for storing said majority signals and for providing said majority signals with a particular delay; second means for comparing said delayed majority signals with an undelayed version of said majority signals and for providing one signal when the delayed and undelayed majority signals are the same and another signal when the delayed and undelayed majority signals are different; counter means responsive to said one signal for incrementing a count and responsive to said other signal for resetting said count to an initial value; and means responsive to a specified count in said counter means and to the majority signals stored in said storage and delay means for providing a signal corresponding to a decoded version of said code.

Claim 15

A detector for detecting the presence of an incoming repetitive code, said code comprising N bits of digital information, said detector comprising: first signal delay means for providing said N bits of said incoming code with a first time delay; second signal delay means for providing said N bits of said incoming code with a second time delay; means for providing an underlayed version of said incoming code; first means for compraing the corresponding bits in said repetitive code between any tow of: (a) said undelayed version of said code; (b) the version of said code having said first time delay; and (c) the version of said code having said second time delay, said comparing means providing first, second and third intermediate signals, respectively resulting from the comparisons of any two of (a), (b) and (c), said first comparing means further comprising means responsive to said first, second and third intermediate signals for providing a majority signal corresponding to the majority vote as to the nature of the bits in (a), (b) and (c); signal storage and delay means for storing said majority signals and for providing said majority signals with a particular delay; second means for comparing said delayed majority signals with an undelayed version of said majority signals and for providing one signal when the delayed and undelayed majority signals are the same and another signal when the delayed and undelayed majority signals are different; counter means responsive to said one signal for incrementing a count and responsive to said other signal for resetting said count to an initial value; and means responsive to a specified count in said counter means and to the majority signals stored in said storage and delay means for providing a signal corresponding to a decoded version of said code.

Claim 16

The detector according to claim 12 wherein said first and second delay means comprise first and second serially connected shift registers and wherein said first and second time delays are equal to each other and wherein each of said registers accommodates M N bits, where M is a positive integer greater than one.

Claim 17

The detector according to claim 13 wherein said first means for comparing comprises; first, second and third AND gated each having two input terminals and an output terminal, said first AND gate being responsive to said underlayed version of said code and the version of said code from said first shift register for providing said first intermediate signal, said second AND gate being responsive to said undelayed version of said code and the version of said code from said second shift register for providing said second intermediate signal, said third AND gate being responsive to the versions of said code from the first and second shift registers for providing said third intermediate signal; and an OR gate having three input terminals and an output terminal, said or gate being responsive to said first, second and third intermediate signal for providing at the output terminal thereof said majority signal.

Claim 18

The detector according to claim 14 wherein said signal storage and delay means comprises an N bit shift register and wherein said second comparing means comprises an exclusive OR gate.

Claim 19

The detector according to claim 15 wherein said count responsive means comprises a read only memory, said memory being addressed from said N bit shigt register in response to said specified count in said counter means.