Patent US3862441A successfully refreshed from Google Patents.
US3862441A
Expired / Lapsed
US
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Mos-fet timing circuit
Assignee: Mitsubishi Electric Corp
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Filing: 1973-11-21
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Granted: 1975-01-21
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Expires: 1993-11-21
Abstract
Abstract A timing circuit for accurately measuring a certain time interval after an engine stops. The circuit comprises a compensation-type MOS-FET device which includes an n-channel MOSFET and a p-channel MOS-FET with common drain and gate connections as the output and inputs to the device. The circuit further includes a condenser and resistor connected to the input of the compensation MOS-FET device. The ratio of the mutual conductance of the n-channel MOS-FET to the mutual conductance of the p-channel MOS-FET is selected to be greater than 10 or less than 0.1, whereby the timing output may be accurately determined by the time constant of the resistor and condenser.
Inventors
- 👤 Hiroshi Nabetani
- 👤 Atsushi Ueda
- 👤 Kousaku Uota
- 👤 Mitsuaki Ishii
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 18:39
CPC Classifications
H; H03; H03K; H03K17/00; H03K17/28; H03K17/284
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
124 words
A timing circuit, which comprises: a d.c. power source; a compensation-type MOS-FET comprising a p-channel MOS-FET and an n-channel MOS-FET having interconnecting gates and drains as the input and output points thereof, the source of said pchannel MOS-FET connected to said d.c. power source; a resistor and a condenser each connected in parallel with said input point of said compensation-type MOS-FET; a second n-channel MOS-FET whose gate is connected to said d.c. power source, whose drain is connected to said resistor and capacitor, and whose source is connected to said input point of said compensation-type MOS-FET; and wherein the ratio of the mutual conductance of said n-channel MOS-FET to the mutual conductance of said p-channel MOS-FET is higher than 10 or lower than 0.1.
Claim 2
Dependent Claim
124 words
A timing circuit, which comprises: a d.c. power source; a compensation-type MOS-FET comprising a p-channel MOS-FET and an n-channel MOS-FET having interconnecting gates and drains as the input and output points thereof, the source of said pchannel MOS-FET connected to said d.c. power source; a resistor and a condenser each connected in parallel with said input point of said compensation-type MOS-FET; a second n-channel MOS-FET whose gate is connected to said d.c. power source, whose drain is connected to said resistor and capacitor, and whose source is connected to said input point of said compensation-type MOS-FET; and wherein the ratio of the mutual conductance of said n-channel MOS-FET to the mutual conductance of said p-channel MOS-FET is higher than 10 or lower than 0.1.
Claim 3
Dependent Claim
216 words
A timing circuit comprising a compensation-type MOS-FET having an input and an output, said compensation-type MOS-FET further including a p-channel MOS-FET having a source, a drain and a gate, said compensation-type MOS-FET further including an n-channel MOS-FET having a source, a drain and a gate, a capacitor, a resistor, a diode, a switch, means connecting the drain of said p-channel MOS-FET and the drain of said n-channel MOS-FET to said output point, means connecting the gate of said p-channel MOS-FET and the gate of said n-channel MOS-FET to said input point, means connecting the source of said p-channel MOS-FET to a power source, means connecting the source of said n-channel MOS-FET to ground, means connecting said capacitor between said input point and ground, means connecting said resistor between said input point and ground, means connecting said diode between said resistor and said switch, means connecting said switch to the power source, the ratio of the mutual conductance of said p-channel MOS-FET to the mutual conductance of said n-channel MOS-FET being greater than 10, whereby a voltage applied to said input point which is a fraction of the power source voltage is sufficient to keep said compensation-type MOS-FET turned on for a predetermined period after said switch is closed and while said capacitor discharges into said resistor.
Claim 4
Dependent Claim
216 words
A timing circuit comprising a compensation-type MOS-FET having an input and an output, said compensation-type MOS-FET further including a p-channel MOS-FET having a source, a drain and a gate, said compensation-type MOS-FET further including an n-channel MOS-FET having a source, a drain and a gate, a capacitor, a resistor, a diode, a switch, means connecting the drain of said p-channel MOS-FET and the drain of said n-channel MOS-FET to said output point, means connecting the gate of said p-channel MOS-FET and the gate of said n-channel MOS-FET to said input point, means connecting the source of said p-channel MOS-FET to a power source, means connecting the source of said n-channel MOS-FET to ground, means connecting said capacitor between said input point and ground, means connecting said resistor between said input point and ground, means connecting said diode between said resistor and said switch, means connecting said switch to the power source, the ratio of the mutual conductance of said p-channel MOS-FET to the mutual conductance of said n-channel MOS-FET being greater than 10, whereby a voltage applied to said input point which is a fraction of the power source voltage is sufficient to keep said compensation-type MOS-FET turned on for a predetermined period after said switch is closed and while said capacitor discharges into said resistor.
Claim 5
Dependent Claim
147 words
A timing circuit comprising a compensation-type MOS-FET having an input and an output, said compensation-type MOS-FET further including a p-channel MOS-FET and a n-channel MOS-FET, a capacitor, a resistor, a transistor, a switch, means connecting said capacitor between said input point and ground, means connecting said resistor between said input point and a power source, means connecting the gate of said transistor to said switch and to said power source and means connecting the output of said transistor to said input point, means connecting said switch to the power source, the ratio of the mutual conductance of said p-channel MOS-FET to the mutual conductance of said n-channel MOS-FET being less than 0.1, whereby said compensation-type MOS-FET remains turned off for a predetermined period after said switch is closed until the voltage built up on said capacitor approaches the power source voltage thereby turning on said compensation-type MOS-FET.
Claim 6
Dependent Claim
147 words
A timing circuit comprising a compensation-type MOS-FET having an input and an output, said compensation-type MOS-FET further including a p-channel MOS-FET and a n-channel MOS-FET, a capacitor, a resistor, a transistor, a switch, means connecting said capacitor between said input point and ground, means connecting said resistor between said input point and a power source, means connecting the gate of said transistor to said switch and to said power source and means connecting the output of said transistor to said input point, means connecting said switch to the power source, the ratio of the mutual conductance of said p-channel MOS-FET to the mutual conductance of said n-channel MOS-FET being less than 0.1, whereby said compensation-type MOS-FET remains turned off for a predetermined period after said switch is closed until the voltage built up on said capacitor approaches the power source voltage thereby turning on said compensation-type MOS-FET.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-01-20 | 1978-07-22 | 1979-01-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-01-20 | 1982-07-22 | 1983-01-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-01-20 | 1986-07-22 | 1987-01-21 | $7700.00 | Window Closed / Lapsed |