Time delay after de-energization circuit

Claim 2

A timer circuit comprising: a. a pair of input terminals connectable to a power supply for supplying direct current to the circuit; b. timer means including resistor means, a capacitor, a field effect transistor and voltage level detector means; c. said resistor means connected in circuit relationship with said pair of input terminals for connection across said power supply, said resistor means further connected in circuit relationship with said capacitor for controlling the rate of discharge of said capacitor; d. said field effect transistor connected in circuit relationship with said capacitor for amplifying linearly the voltage from said capacitor, said field effect transistor further connected in circuit relationship with said voltage level detector means for providing a linear voltage output to said voltage level detector means corresponding to the charge on said capacitor; e. said voltage level detector means having a first condition wherein an output is provided therefrom for transmission to a controlled circuit and a second condition wherein no output is provided therefrom; and f. said timer means providing a first timed interval during which upon the occurrence of a loss of power to the timer circuit with said voltage level detector means in said first condition said output from said voltage level detector means continues until the elapsed time of said loss of power exceeds said first timed interval.

Claim 3

A timer circuit as set forth in claim 1 wherein: a. said resistor means includes a resistor having a value preselected to cause said capacitor to discharge at a predetermined rate; and b. said first timed interval corresponds to the elapsed time for said capacitor to discharge to a predetermined level.

Claim 4

A timer circuit as set forth in claim 1 wherein: a. said field effect transistor comprises an enhancement mode metal oxide semiconductor field effect transistor; and b. said voltage level detector means comprises a controlled hysteresis network including first and second transistors and a plurality of resistors connected in circuit relationship such that when said first transistor is in an ON condition said second transistor is in an OFF condition and said voltage level detector means is in said first condition, and when said first transistor is in an OFF condition said second transistor is in an ON condition and said voltage level detector means is in said second condition.

Claim 5

A timer circuit as set forth in claim 1 wherein: a. said voltage level detector means is caused to move from said first condition to said second condition upon the occurrence of a loss of power to the timer circuit which exceeds the elapsed time of said first timed interval; and b. said timer means provides a second timed interval following which said voltage level detector means is caused to move from said second condition to said first condition to thereby once again cause said voltage level detector means to provide an output therefrom when power of said timer circuit is reinstated.

Claim 6

A timer circuit as set forth in claim 4 further comprising: a. switch means connected in circuit relationship with said pair of input terminals; b. said second timed interval corresponding to the elapsed time for said capacitor to recharge; and c. said second timed interval being initiated in response to operation of said switch means.

Claim 7

A timer circuit comprising: a. a pair of input terminals connectable to a power supply for supplying direct current to the circuit; b. time delay means including resistor means, a capacitor, an enhancement mode field effect transistor and voltage level detector means; c. said resistor means connected in circuit with said pair of input terminals for connection across said power supply, said resistor means further connected in circuit relationship with said capacitor for controlling the rate of discharge of said capacitor; d. said enhancement mode field effect transistor connected in circuit relationship with said capacitor for amplifying the voltage from said capacitor, said enhancement mode field effect transistor further connected in circuit relationship with said voltage level detector means for providing a voltage output to said voltage level detector means corresponding to the charge on said capacitor; e. said voltage level detector means having a first condition wherein an output is provided therefrom for transmission to a controlled circuit and a second condition wherein no output is provided therefrom; f. said time delay means providing a first timed interval during which upon the occurrence of a loss of power to the timer circuit with said voltage level detector means in said first condition said output from said voltage level detector means continues until the elapsed time of said loss of power exceeds said first timed interval; and g. said first timed interval corresponds to the elapsed time for said capacitor to discharge to a predetermined level.

Claim 8

A timer circuit comprising: a. a pair of input terminals connectable to a power supply for supplying direct current to the circuit; b. time delay means including resistor means, a capacitor, an enhancement mode field effect transistor and voltage level detector means; c. said resistor means connected in circuit with said pair of input terminals for connection across said power supply, said resistor means further connected in circuit relationship with said capacitor for controlling the rate of discharge of said capacitor; d. said enhancement mode field effect transistor connected in circuit relationship with said capacitor for amplifying the voltage from said capacitor, said enhancement mode field effect transistor further connected in circuit relationship with said voltage level detector means for providing a voltage output to said voltage level detector means corresponding to the charge on said capacitor; e. said voltage level detector means having a first condition wherein an output is provided therefrom for transmission to a controlled circuit and a second condition wherein no output is provided therefrom; f. said time delay means providing a first timed interval during which upon the occurrence of a loss of power to the timer circuit with said voltage level detector means in said first condition said output from said voltage level detector means continues until the elapsed time of said loss of power exceeds said first timed interval; and g. said first timed interval corresponds to the elapsed time for said capacitor to discharge to a predetermined level.

Claim 9

A timer circuit as set forth in claim 6 wherein: a. said enhancement mode field effect transistor comprises a metal oxide semiconductor field effect transistor; and b. said voltage level detector means comprises a Schmitt trigger circuit.

Claim 10

A timer circuit as set forth in claim 6 wherein: a. said voltage level detector means is caused to move from said first condition to said second condition upon the occurrence of a loss of power to the timer circuit which exceeds the elapsed time of said first timed interval; and b. said time delay means provides a second timed interval following which said voltage level detector means is caused to move from said second condition to said first condition to thereby once again cause said voltage level detector means to provide an output therefrom.

Claim 11

A timer circuit for timing loss of power comprising: a. a pair of input terminals connectable to a power supply for supplying direct current to the circuit; b. time delay means including resistor means, a capacitor, an enhancement mode field effect transistor and a controlled hysteresis network; c. said resistor meanS connected in circuit with said pair of input terminals for connection across said power supply, said resistor means further connected in circuit relationship with said capacitor for controlling the rate of discharge of said capacitor; d. said enhancement mode field effect transistor connected in circuit relationship with said capacitor for amplifying the voltage from said capacitor, said enhancement mode field effect transistor further connected in circuit relationship with said controlled hysteresis network for providing a voltage output to said controlled hysteresis network corresponding to the charge on said capacitor; e. said controlled hysteresis network having a first condition wherein an output is provided therefrom for transmission to a controlled circuit and a second condition wherein no output is provided therefrom; f. said controlled hysteresis network including first and second transistors and a plurality of resistors connected in circuit relationship such that when said first transistor is in an ON condition said second transistor is in an OFF condition and said controlled hysteresis network is in said first condition, and when said first transistor is in an OFF condition said second transistor is in an ON condition and said controlled hysteresis network is in said second condition; g. said time delay means providing a first timed interval during which upon the occurrence of a loss of power to the timer circuit with said controlled hysteresis network in said first condition said output from said controlled hysteresis network continues until the elapsed time of said loss of power exceeds said first timed interval; h. said first timed interval corresponding to the elapsed time for said capacitor to discharge to a predetermined level; i. said controlled hysteresis network being caused to move from said first condition to said second condition upon the occurrence of a loss of power to the timer circuit which exceeds the elapsed time of said first timed interval; j. said time delay means further providing a second timed interval following which said controlled hysteresis network is caused to move from said second condition to said first condition to thereby once again cause said controlled hysteresis network to provide an output therefrom; and k. said second timed interval corresponding to the elapsed time for said capacitor to recharge.

Claim 12

A timer circuit for timing loss of power comprising: a. a pair of input terminals connectable to a power supply for supplying direct current to the circuit; b. time delay means including resistor means, a capacitor, an enhancement mode field effect transistor and a controlled hysteresis network; c. said resistor meanS connected in circuit with said pair of input terminals for connection across said power supply, said resistor means further connected in circuit relationship with said capacitor for controlling the rate of discharge of said capacitor; d. said enhancement mode field effect transistor connected in circuit relationship with said capacitor for amplifying the voltage from said capacitor, said enhancement mode field effect transistor further connected in circuit relationship with said controlled hysteresis network for providing a voltage output to said controlled hysteresis network corresponding to the charge on said capacitor; e. said controlled hysteresis network having a first condition wherein an output is provided therefrom for transmission to a controlled circuit and a second condition wherein no output is provided therefrom; f. said controlled hysteresis network including first and second transistors and a plurality of resistors connected in circuit relationship such that when said first transistor is in an ON condition said second transistor is in an OFF condition and said controlled hysteresis network is in said first condition, and when said first transistor is in an OFF condition said second transistor is in an ON condition and said controlled hysteresis network is in said second condition; g. said time delay means providing a first timed interval during which upon the occurrence of a loss of power to the timer circuit with said controlled hysteresis network in said first condition said output from said controlled hysteresis network continues until the elapsed time of said loss of power exceeds said first timed interval; h. said first timed interval corresponding to the elapsed time for said capacitor to discharge to a predetermined level; i. said controlled hysteresis network being caused to move from said first condition to said second condition upon the occurrence of a loss of power to the timer circuit which exceeds the elapsed time of said first timed interval; j. said time delay means further providing a second timed interval following which said controlled hysteresis network is caused to move from said second condition to said first condition to thereby once again cause said controlled hysteresis network to provide an output therefrom; and k. said second timed interval corresponding to the elapsed time for said capacitor to recharge.

Claim 13

A timer circuit for timing loss of power as set forth in claim 9 further comprising: a. switch means connected in circuit relationship with said pair of input terminals; and b. said second timed interval being initiated in response to operation of said switch means.