Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
212 words
A system for the transfer of information relating to the point of time and direction of transitions between two states of a biphase input signal comprising: a transmitting means including, means to scan said biphase input signal at a fixed repetition rate, and encoding means responsive to said scanning means and having means representing said input signal in a code word having a plurality of bits indicating the direction of transition and at least one bit indicating the time of occurrence of the transition relative to a fixed pattern of repetitIon time intervals, wherein the fixed pattern is repeated at a selected multiple of the repetition time intervals; and a receiving means including, shift register means having an input and a plurality of stages receiving the code word and additionally having one stage in excess of the number of bits in the code word, output means for generating a biphase output signal, and logic circuit means connected to said shift register stages for controlling the state of said output means in accordance with the code word bits in said shift register stages, said logic circuit means being capable of effecting a majority decision as regards a plurality of shift register stages including said excess stage to ascertain the direction of the transition.
Claim 2
Independent Claim
212 words
A system for the transfer of information relating to the point of time and direction of transitions between two states of a biphase input signal comprising: a transmitting means including, means to scan said biphase input signal at a fixed repetition rate, and encoding means responsive to said scanning means and having means representing said input signal in a code word having a plurality of bits indicating the direction of transition and at least one bit indicating the time of occurrence of the transition relative to a fixed pattern of repetitIon time intervals, wherein the fixed pattern is repeated at a selected multiple of the repetition time intervals; and a receiving means including, shift register means having an input and a plurality of stages receiving the code word and additionally having one stage in excess of the number of bits in the code word, output means for generating a biphase output signal, and logic circuit means connected to said shift register stages for controlling the state of said output means in accordance with the code word bits in said shift register stages, said logic circuit means being capable of effecting a majority decision as regards a plurality of shift register stages including said excess stage to ascertain the direction of the transition.
Claim 3
Dependent Claim
51 words
The system according to claim 1 wherein the number of bits of the code word does not exceed the number of scannings at said fixed repetition rate per shortest time interval to be expected between transitions of the biphase input signal divided by the selected multiple of the repetition time intervals.
Claim 4
Dependent Claim
24 words
The system according to claim 2 wherein said scanning means includes a shift register having a stage for each bit of the code word.
Claim 5
Dependent Claim
43 words
The system according to claim 3 wherein said encoding means includes a plurality of gates adapted to control at least one stage of the scanning means shift register to assume said at least one bit indicating the time of occurrence of the transition.
Claim 6
Dependent Claim
75 words
The system according to claim 4 wherein said encoding means includes a trigger means responsive to a transition of the input signal in one direction for setting a plurality of said scanning means shift register stages with code word bits in accordance therewith, and another trigger means responsive to a transition of the input signal in another direction for resetting said plurality of scanning means shift register stages with code word bits in accordance therewith.
Claim 7
Dependent Claim
30 words
The system according to claim 3 including a divider circuit means for stepping along the shift register of the scanning means in response to a predetermined number of clock pulses.
Claim 8
Dependent Claim
25 words
The system according to claim 3 including an output transmitting stage connected to the shift register for transmitting the code word to the receiving means.
Claim 9
Dependent Claim
30 words
The system according to claim 1 including trigger means responsive to the occurrence of transitions of the biphase output signal for controlling some of the stages of the shift register.
Claim 10
Dependent Claim
26 words
The system according to claim 1 including a clock controlled divider means for stepping the shift register in accordance with a predetermined number of clock pulses.