Patent US3858237A successfully refreshed from Google Patents.
US3858237A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor integrated circuit isolated through dielectric material
Assignee: Toshiba Corp
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Filing: 1973-05-09
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Granted: 1974-12-31
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Expires: 1993-05-09
Abstract
Abstract A semiconductor integrated circuit includes a plurality of semiconductor elements formed on one side of a substrate. The semiconductor element is surrounded by a dish-like outer dielectric layer so as to be insulated from the substrate, and includes therein a bottomless inner dielectric layer adjacent to the outer dielectric layer. A PN junction is formed in the region enclosed by the inner layer with the peripheral edge located thereat.
Inventors
- 👤 K Niwa
- 👤 E Inaba
- 👤 H Tsutsumi
- 👤 Y Sumitomo
- 👤 H Sawazaki
- 👤 K Sakai
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 17:03
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/20; H10D; H10D99/00; H10W10/00; H10W10/01; H10W10/011; H10W10/019; H10W10/10; Y; Y10; Y10S; Y10S148/00; Y10S148/051; Y10S148/085; Y10S148/122; Y10S438/00; Y10S438/977
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
175 words
A SEMICONDUCTOR INTERGREATED CIRCUIT COMPRISING; A SUPPORT SUBSTRATE (11); A PLURALITY OF BOTTOMED ENCLOSED OUTER DIELECTRIC LAYERS (12) WHOSE ONE END IS OPEN AT ONE SURFACE OF THE SUPPORT SUBSTRATE (11), SAID BOTTOMED OUTER DIELECTRIC LAYERS (12) HAVING SUBSTANTIALLY NO DISCONTINUITIES THEREIN OTHER THAN THE ONE OPEN END; A BOTTOMLESS INNER DIELECTRIC LAYER (13) FORMED WITHIN AND ADJACNT TO THE OUTER DIELECTRIC LAYER (12); AND AN ISLAND REGION (10) HAVING; AN OUTER SEMICONDUCTOR REGION (14) OF POLYCRYSTALLINE MATRIAL DEFINED BETWEEN THE INNER AND OUTER DIELECTRIC LAYERS (13,12); AND AN INNER SEMICONDUCTOR REGION (24,25,26) OF MONOCRYSTALLINE MATERIAL WITHIN THE INNER DIELECTRIC LAYER (13); A TRAISISTOR ELEMENT (16) BEING FORMED IN SAID ISLAND REGION (10) AND HAVING ELECTRODES WHICH ARE POSITIONED ON SAID ONE SURFACE OF SAID SUBSTRATE (11), SAID TRANSISTOR ELEMENT (16) COMPRISING: A BASE REGION (25) OF ONE CONDUCTIVITY TYPE AND SITUATED WITHIN SAID INNER DIELECTRIC LAYER (13); A COLLECTOR REGION (24) OF THE OTHER CONDUCTIVITY TYPE AND INCLUDING A PORTION (15) SITUATED WITHIN SAID INNER DLELECTRIC LAYER (13), SAID COLLECTOR REGION (24) FURTHER INCLUDING
Claim 2
Dependent Claim
175 words
A SEMICONDUCTOR INTERGREATED CIRCUIT COMPRISING; A SUPPORT SUBSTRATE (11); A PLURALITY OF BOTTOMED ENCLOSED OUTER DIELECTRIC LAYERS (12) WHOSE ONE END IS OPEN AT ONE SURFACE OF THE SUPPORT SUBSTRATE (11), SAID BOTTOMED OUTER DIELECTRIC LAYERS (12) HAVING SUBSTANTIALLY NO DISCONTINUITIES THEREIN OTHER THAN THE ONE OPEN END; A BOTTOMLESS INNER DIELECTRIC LAYER (13) FORMED WITHIN AND ADJACNT TO THE OUTER DIELECTRIC LAYER (12); AND AN ISLAND REGION (10) HAVING; AN OUTER SEMICONDUCTOR REGION (14) OF POLYCRYSTALLINE MATRIAL DEFINED BETWEEN THE INNER AND OUTER DIELECTRIC LAYERS (13,12); AND AN INNER SEMICONDUCTOR REGION (24,25,26) OF MONOCRYSTALLINE MATERIAL WITHIN THE INNER DIELECTRIC LAYER (13); A TRAISISTOR ELEMENT (16) BEING FORMED IN SAID ISLAND REGION (10) AND HAVING ELECTRODES WHICH ARE POSITIONED ON SAID ONE SURFACE OF SAID SUBSTRATE (11), SAID TRANSISTOR ELEMENT (16) COMPRISING: A BASE REGION (25) OF ONE CONDUCTIVITY TYPE AND SITUATED WITHIN SAID INNER DIELECTRIC LAYER (13); A COLLECTOR REGION (24) OF THE OTHER CONDUCTIVITY TYPE AND INCLUDING A PORTION (15) SITUATED WITHIN SAID INNER DLELECTRIC LAYER (13), SAID COLLECTOR REGION (24) FURTHER INCLUDING
Claim 3
Dependent Claim
24 words
A semiconductor integrated circuit as claimed iln claim 1 in which said PN junction is parallel to the top surface of the support substrate.
Claim 4
Dependent Claim
20 words
A semiconductor integrated circuit as claimed in claim 1 in which said inner dielectric layer has a bottomless plate shape.
Claim 5
Dependent Claim
25 words
A semiconductor integrated circuit as claimed in claim 1 in which said outer semiconductor region has a uniform distribution of impurities doped in high concentration.
Claim 6
Dependent Claim
44 words
A semiconductor integrated circuit as claimed in claim 1 in which said outer dielectric layer has a peripheral side portion inclined in the same direction as that of the inner dielectric layer and a bottom portion parallel to the top surface of the substrate.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-12-30 | 1978-07-01 | 1978-12-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-12-30 | 1982-07-01 | 1982-12-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-12-30 | 1986-07-01 | 1986-12-31 | $7700.00 | Window Closed / Lapsed |