Patent US3854036A successfully refreshed from Google Patents.
US3854036A
Expired / Lapsed
US
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Tag reader to digital processor interface circuit
Assignee: Singer Co
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Filing: 1974-02-27
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Granted: 1974-12-10
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Expires: 1994-02-27
Abstract
Abstract Circuitry particularly suitable as an interface between a merchandise tag reader, or the like, and a digital computer. Tag readers which may be used by store clerks or market checkers to read the merchandise code printed on a product or label may be operated over vast ranges, e.g., between four and sixty inches per second. In most cases, depending upon the code used, the bit value of a pulse read over this range of speed can only be determined by comparing the width of a pulse with the width of an adjacent pulse. The disclosed circuitry produces compressed digital data by generating a binary number representing the logarithm of the width of each pulse so that a required ratio of present to previous pulse widths can easily be obtained by a simple subtraction process.
Inventors
- 👤 G Gupta
- 👤 J Hunt
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 14:11
CPC Classifications
G; G01; G01R; G01R29/00; G01R29/02; G01R29/027; G01R29/0273; G06; G06F; G06F1/00; G06F1/02; G06F1/03; G06F1/0307; G06K; G06K7/00; G06K7/01; G06K7/016; G06K7/0166; G07; G07G; G07G1/00; G07G1/10
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
108 words
Circuitry for determining the values of binary signal pulses serially introduced to the circuitry at varying speeds and pulse widths, said circuitry comprising: input means for receiving the binary signal pulses; counting means coupled to said input means for generating a count signal representing the width of each one of said pulses; converting means coupled to said counting means and responsive to said count signal for generating a number representing the logarithm of said count signal; and comparison means coupled to said converting means for comparing the logarithmic number generated for each binary signal pulse with the number generated for a neighboring binary signal pulse of known value.
Claim 2
Dependent Claim
108 words
Circuitry for determining the values of binary signal pulses serially introduced to the circuitry at varying speeds and pulse widths, said circuitry comprising: input means for receiving the binary signal pulses; counting means coupled to said input means for generating a count signal representing the width of each one of said pulses; converting means coupled to said counting means and responsive to said count signal for generating a number representing the logarithm of said count signal; and comparison means coupled to said converting means for comparing the logarithmic number generated for each binary signal pulse with the number generated for a neighboring binary signal pulse of known value.
Claim 3
Dependent Claim
33 words
The circuitry claimed in claim 1 wherein said comparison means compares by subtracting the logarithmic number generated for a binary signal pulse with the number generated for the next previous binary signal pulse.
Claim 4
Dependent Claim
37 words
The circuitry claimed in claim 1 wherein said counting means includes a clock, a linear counter, and first gating means for gating the clock signal and each binary signal pulse to the input of said linear counter.
Claim 5
Dependent Claim
61 words
The circuitry claimed in claim 1 wherein said converting means includes a read-only-memory constructed to generate output pulses according to the equation: Po K log (Pi - c); wherein Po number of output pulses; Pi number of input counts from said counting means; K constant; and c desired number of input counts before the first output pulse is to be generated.
Claim 6
Dependent Claim
62 words
The circuitry claimed in claim 3 wherein said converting means includes a read-only-memory having a plurality of output lines, and a multiplexer coupled to said plurality and controlled by the state of at least one of the more significant counts of said linear counter for passing in series through said multiplexer the logarithmic count appearing on each output line of said plurality.
Claim 7
Dependent Claim
84 words
The circuitry claimed in claim 3 further including a frequency dividing circuit coupled to said clock for dividing the clock frequency by an integer, and second gating means coupled to said dividing circuit, to said input means, to said first gating means, and to one of the more significant count terminals of said linear counter for disabling said first gating means and for reducing the counting frequency of said linear counter when the count in said counter has enabled said more significant count terminal.
Claim 8
Dependent Claim
16 words
The circuitry claimed in claim 3 wherein said input means includes amplifying and pulse shaping circuitry.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-12-09 | 1978-06-10 | 1978-12-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-12-09 | 1982-06-10 | 1982-12-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-12-09 | 1986-06-10 | 1986-12-10 | $7700.00 | Window Closed / Lapsed |