Patent US3853496A successfully refreshed from Google Patents.
US3853496A
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Method of making a metal insulator silicon field effect transistor (mis-fet) memory device and the product
Assignee: General Electric Co
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Filing: 1973-01-02
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Granted: 1974-12-10
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Expires: 1993-01-02
Abstract
Abstract The present invention relates to the method of making a memory device of the metal insulator silicon field effect transistor structure having a gate region combining a chemically formed thin oxide layer and a second insulating layer, such as silicon nitride, and to the novel product which results from this method. The method entails the step of chemically oxidizing the surface of the silicon channel region by a self-limiting process to form a thin porous oxide, and a nitriding step which is conducted under conditions producing optimum interface traps and minimum initial charge. Both steps lead to highly reproducible devices. The method is readily applied to large arrays of devices, offering ease of manufacture and close device parameter control. One form of the process provides for the production of both memory and read-out devices appropriate in an array.
Inventors
- 👤 M Kim
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 16:52
CPC Classifications
H; H10; H10P; H10P14/00; H10P14/60; H10P14/69; H10P14/694; H10P14/6943; H10P14/69433; G; G11; G11C; G11C16/00; G11C16/02; G11C16/04; G11C16/0466; H10D; H10D30/00; H10D30/60; H10D30/69; H10D64/00; H10D64/01; H10D64/031; H10D64/035; H10P14/63; H10P14/6302; H10P14/6304; H10P14/6306; H10P14/6308; H10P14/6309; H10P14/6322; H10P14/6326; H10P14/6328; H10P14/6334; H10P14/66; H10P14/662; H10P14/668; H10P14/6681; H10P14/6682; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0144; H10P14/692; H10P14/6921; H10P14/69215
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
139 words
THE METHOD OF MAKING A METAL INSULATION SILICON FIELD EFFECT TRANSISTOR (MIS-FET) MEMORY DEVICE, COMPRISING THE STEPS OF: A. FORMING AN INSULATING SIO2 LAYER OVER A LOW RESISTIVITY SUBSTRATE, B. ETCHING OPENING IN SAID SIO2 LAYER AND DIFFUSING THE SOURCE AND DRAIN REGIONS, C. SEALING SAID SOURCE AND DRAIN REGIONS WITH SIO2 AND OPENING AN INTERMEDICATE CHANNEL REGION, D. IMMERSING THE SUBSTRATE IN CONCENTRATED NITRIC ACID TO FROM A LOW TEMPERATURE CHEMICAL OXIDE OF SILICON OVER SAID CHANNEL REGION UNDER SELF-LIMITING CONDITIONS IN ORDER TO PRODUCE A FIRST INSULATING LAYER ABOUT 20A IN THICKNESS, E. FORMING A SECOND INSULATION LAYER OVER SAID CHEMICAL OXIDE TO PREVENT A REGION OF DEEP TRAPS AT THEIR INTERFACE, F. OPENING SAID SOURCE AND DRAIN CONTACT REGIONS, AND G. METALLIZING SAID SOURCE AND DRAIN REGIONS AND SAID SECOND INULATING LAYER OVER SECOND CHANNEL REGION.
Claim 2
Independent Claim
139 words
THE METHOD OF MAKING A METAL INSULATION SILICON FIELD EFFECT TRANSISTOR (MIS-FET) MEMORY DEVICE, COMPRISING THE STEPS OF: A. FORMING AN INSULATING SIO2 LAYER OVER A LOW RESISTIVITY SUBSTRATE, B. ETCHING OPENING IN SAID SIO2 LAYER AND DIFFUSING THE SOURCE AND DRAIN REGIONS, C. SEALING SAID SOURCE AND DRAIN REGIONS WITH SIO2 AND OPENING AN INTERMEDICATE CHANNEL REGION, D. IMMERSING THE SUBSTRATE IN CONCENTRATED NITRIC ACID TO FROM A LOW TEMPERATURE CHEMICAL OXIDE OF SILICON OVER SAID CHANNEL REGION UNDER SELF-LIMITING CONDITIONS IN ORDER TO PRODUCE A FIRST INSULATING LAYER ABOUT 20A IN THICKNESS, E. FORMING A SECOND INSULATION LAYER OVER SAID CHEMICAL OXIDE TO PREVENT A REGION OF DEEP TRAPS AT THEIR INTERFACE, F. OPENING SAID SOURCE AND DRAIN CONTACT REGIONS, AND G. METALLIZING SAID SOURCE AND DRAIN REGIONS AND SAID SECOND INULATING LAYER OVER SECOND CHANNEL REGION.
Claim 3
Dependent Claim
40 words
The method of claim 1 wherein during formation of said chemical oxide, the concentration of said nitric acid is in excess of 60 percent by weight and maintained at a constant temperature, said reaction continuing for at least 20 minutes.
Claim 4
Dependent Claim
19 words
The method of claim 2 wherein said constant temperature is set at the boiling point of said nitric acid.
Claim 5
Dependent Claim
19 words
The method of claim 3 wherein said acid is 84 percent by weight and said boiling point is 86*C.
Claim 6
Dependent Claim
58 words
The method of claim 1 wherein said second insulating layer is silicon nitride, said formation occuring by reacting a mixture of NH3 with a small amount of SiH4 at a temperature of from 750*C to 850*C to minimize the fixed charge therein, and the upper limit favoring the formation of the amorphous form of nitride, and avoiding crystallinity
Claim 7
Dependent Claim
25 words
The method of claim 1 wherein said second insulating layer is Al2O3 formed by hydrolyzing AlCl3 in a mixture of H2 and CO2 at 900*C.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-12-09 | 1978-06-10 | 1978-12-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-12-09 | 1982-06-10 | 1982-12-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-12-09 | 1986-06-10 | 1986-12-10 | $7700.00 | Window Closed / Lapsed |