Three masking step process for fabricating insulated gate field effect transistors

Claim 2

A process according to claim 2 wherein said semiconductor substrate is made of silicon, said thin gate insulator comprises a laminate of grown silicon dioxide and silicon nitride, and said thick field insulator comprises pyrolytically deposited silicon dioxide.

Claim 3

A three resist-masking step process for fabricating an integrated circuit insulated gate field effect transistor comprising the steps of depositing on one surface of a silicon substrate of one conductivity type thin gate insulating layers of grown silicon dioxide and silicon nitride, and an overlying thick field silicon dioxide layer, applying a first patterned photoresist mask and etching source and drain openings through said insulating layers down to the substrate surface, preparing the processed substrate for diffusion by depositing a coating of activator impurity and glass at least in said source and drain openings, and thermally diffusing the activator impurity into said silicon substrate to form opposite conductivity type source and drain electrodes, applying a second patterned photoresist mask and simultaneously etching source and drain contact holes and a gate opening therebetween using said silicon nitride layer as an etch stop, depositing a metallization layer over the entire surface of the processed substrate, and applying a third patterned photoresist mask and etching said metallization layer into electrically isolated source, gate, and drain contact metallizations such that portions of said contact metallizations overlie said thick field silicon dioxide layer, said thick field silicon dioxide layer having sufficient thickness to prevent electrical interference with the underlying transistor, said photoresist masks being removed individually at an appropriate point in the process.