Improved static remote-control relay selection system

Claim 1

In a static remote-control relay which can be controlled by a pulse train including a starting pulse followed by a finite set of possible pulses transmitted at a given frequency, the starting pulse being separated from the first Possible pulse of said finite set of possible pulses by a time differing from the time between two possible pulses of the said finite set of possible pulses, including: means for receiving said finite possible pulse set; a pulse generator responsive to the first starting pulse to start delivering, at an output thereof, pulses in phase with the pulses of the said finite possible pulse set; a counter having a count input connected to said pulse generator for counting pulses generated thereby and a plurality or ordered outputs, the number of said ordered counter outputs being at least as large as the number of possible pulses from the finite set and each said counter output delivering a pulse when the pulse count stored in said counter corresponds to the order of the respective counter output; and a programmable logic circuit having a plurality of inputs respectively connected to the ordered outputs of the said counter, at least one input connected to said pulse train receiving means and a plurality of useful outputs to selectively produce control signals on said useful outputs in response to pulse coincidence on said pulse train receiving means and a predetermined one of said counter outputs, the improvement which comprises a preselection circuit responsive to preselection pulses forming a first part of said finite set of possible pulses for inhibiting said programmable logic circuit when a predetermined preselection pulse is not detected in coincidence with a predetermined count pulse delivered by said counter, said preselection circuit comprising: a first bistable circuit coupled to an output of said programmable logic circuit for memorizing the coincidence of a preselection pulse in said first part of the first set of pulses and of a predetermined count pulse, means coupled to said first bistable circuit and to a predetermined one of said counter ordered outputs having an order higher than that corresponding to the end of said first part of the finite set of possible pulses for detecting the occurrence of a pulse at said predetermined counter output when no coincidence has been memorized by said first bistable circuit, and a second bistable circuit coupled to said detecting means for switching in response to said detected occurrence into a state inhibiting said programmable logic circuit until the end of the finite pulse set.