Programmed pulse switch and control system having same

Claim 2

A programmed pulse switch comprising a pulse source having an output at which appears a train of pulses, wherein said train constitutes alternate on-and-off periods of a signal; a pulse counter, and start/stop circuitry, said start/stop circuitry being actuable to a start condition and, alternately to a stop condition, said circuitry, upon actuation to said start condition, being responsive solely to an ending on-period of said signal to apply said signal, in its next following off-period, to said pulse counter; said pulse counter; being responsive to said signal to count pulses in the form of on-periods of said signal applied thereto immediately following said off-period, said pulse counter being settable to produce a control signal upon counting an arbitrary predetermined number of the last said pulses; said start/stop circuitry being responsive to said control signal to prevent the on-period of signal next following the last of said predetermined number of pulses from being counted by said pulse; said start/stop circuit including an ''''and'''' gate requiring two, like, input pulses for enablement and applying said signal to said counter, said gate being connected to said pulse source for receiving said ending on-period as one said input pulses; said start/stop circuitry including means connected to said gate for providing the other said input pulse, in the form of a signal level change like a said on-period, said means being actuable independently of said stop/start circuitry for producing said level change stepwise and continuously until said control signal is produced, said means being effectively connected to said counter to receive said control signal and being responsive to said control signal to reverse said level change whereby to disable said gate.

Claim 3

In combination with the programmed pulse switch of claim 1, pulse-actuated motive means of a controller for controlling a process with respect to a predetermined control point, said motive means being constructed and arranged for changing said control point in response to pulses of signal applied to said motive means, and in proportion to the number of said pulses applied to said motive means; said start/stop circuitry of said programmed pulse switch being arranged to apply the pulses applied to said pulse counter to said motive means, and to prevent pulses from being applied thereto when in its said stop condition.

Claim 4

The invention of claim 2, including a pair of channels via which said pulses applied to said pulse counter are also applied to said motive means under control of said start/stop circuitry, means for selecting one or the other only of said channels for applying the last said pulses to said motive means; one of said channels being arranged to cause the pulses applied via it to said motive means to have a sense opposite to the sense of pulses applied via the other of said channels to said motive means, and said motive means being constructed and arranged to change said control point in a sense corresponding to the pulses applied to said motive means.

Claim 5

The invention of claim 2, including a pair of channels via which said pulses applied to said pulse counter are also applied to said motive means under control of said start/stop circuitry, means for selecting one or the other only of said channels for applying the last said pulses to said motive means, and said motive means being constructed and arranged to change said control point in a sense corresponding to the channel via which pulses are applied to said motive means.

Claim 6

A programmed pulse switch comprising, a first flip-flop, a first gate means connected to the P-output of said first flip-flop for enabling of said first gate means, a second flip-flop and second gate means, the set input of said second flip-flop being connected to said first gate means to be set by signal received via said first gate means when the same is enabled, said second gate means being connected to the P-output of said second flip-flop for enabling of said second gate means, said first gate means being connected to a continuous pulse generator for receiving said signal in the form of pulses therefrom and applying said pulses, when enabled, to said set input of said second flip-flop, said second gate means being connected to said continuous pulse generator for gating pulses therefrom, when said second gate means is enabled, a third gate means and a pulse counter, said third gate means being connected to said second gate means to be enabled by said pulses when said second gate means is enabled, said third gate means applying said pulses to said pulse counter when said third gate means and said second gate means are both enabled, said pulse counter being responsive to the first pulse following enabling of said second and third gate means to count the last said pulses and the next pulses following it, said pulse counter being settable to generate a control pulse in response to its counting a predetermined number of pulses; a third flip-flop having its Q-output connected to the direct-clear input of said first flip-flop, said third flip-flop having its set input connected to said pulse counter to receive said control pulse and to be set thereby, whereby to prevent resetting said first flip-flop after said control pulse is generated; reset means operable to reset each said flip-flop simultaneously and set means operable to set said first flip-flop.

Claim 7

A programmed pulse switch comprising, a first flip-flop, a first gate means connected to the P-output of said first flip-flop for enabling of said first gate means, a second flip-flop and second gate means, the set input of said second flip-flop being connected to said first gate means to be set by signal received via said first gate means when the same is enabled, said second gate means being connected to the P-output of said second flip-flop for enabling of said second gate means, said first gate means being connected to a continuous pulse generator for receiving said signal in the form of pulses therefrom and applying said pulses, when enabled, to said set input of said second flip-flop, said second gate means being connected to said continuous pulse generator for gating pulses therefrom, when said second gate means is enabled, a third gate means and a pulse counter, said third gate means being connected to said second gate means to be enabled by said pulses when said second gate means is enabled, said third gate means applying said pulses to said pulse counter when said third gate means and said second gate means are both enabled, said pulse counter being responsive to the first pulse following enabling of said second and third gate means to count the last said pulses and the next pulses following it, said pulse counter being settable to generate a control pulse in response to its counting a predetermined number of pulses; a third flip-flop having its Q-output connected to the direct-clear input of said first flip-flop, said third flip-flop having its set input connected to said pulse counter to receive said control pulse and to be set thereby, whereby to prevent resetting said first flip-flop after said control pulse is generated; reset means operable to reset each said flip-flop simultaneously and set means operable to set said first flip-flop.

Claim 8

The invention of claim 5, wherein said pulse counter is responsive to P-output of said second flip-flop to reset to a predetermined value the count of said pulse counter.

Claim 9

The invention of claim 5, wherein said set and reset means is switch means operable to a set condition and, alternately to a reset condition, and being constructed and arranged such that it is possible for said switch means to be in its set condition when said control signal is generated.

Claim 10

In combinatIon, utilization means requiring n whole pulses for actuation, a generator of whole pulses, a counter responsive to pulses to count same, gate means for gating said whole pulses to said counter for counting thereby, and to said utilization means; enabling means connected to receive said whole pulses, and to said gate means; said enabling means being responsive to the trailing edge of the first pulse received thereby to enable said gate means.

Claim 11

In combinatIon, utilization means requiring n whole pulses for actuation, a generator of whole pulses, a counter responsive to pulses to count same, gate means for gating said whole pulses to said counter for counting thereby, and to said utilization means; enabling means connected to receive said whole pulses, and to said gate means; said enabling means being responsive to the trailing edge of the first pulse received thereby to enable said gate means.

Claim 12

The invention of claim 8, wherein said counter is responsive to counting n pulses to produce a control signal upon counting the nth of said pulses, and disabling means connected to receive said control signal, and to said gate means; said disabling means being responsive to said control signal to disable said gate means.

Claim 13

The invention of claim 9, wherein said enabling means is a flip-flop having its P-output connected to said gate means for enabling same when said flip-flop is set, said disabling means being connected to the direct-clear input of said flip-flop and being responsive to said control signal for making said flip-flop disable said gate means. 11 The invention of claim 9, wherein said first enabling means is a first flip-flop, and said disabling means is a second flip-flop; said second flip-flop having its Q-output connected to the direct-clear input of said first flip-flop, said first flip-flop having its P-output connected to said gate means for enabling same, in response to setting said first flip-flop, set second flip-flop having its set input connected to said counter to be set by said control signal.

Claim 14

The invention of claim 9, including a starting flip-flop, wherein said enabling means is connected to the P-output of said starting flip-flop, and also including a stopping flip-flop, said stopping flip-flop having its Q-output connected to said enabling means for allowing same to be enabled by said P-output of said starting flip-flop, said Q-output of said stopping flip-flop being also connected to the direct-clear input of said first flip-flop, and the set input of said stopping flip-flop being connected to said counter to receive said control signal and to be set by said control signal.

Claim 15

A control system having a programmed pulse switch, said programmed pulse switch comprising a pulse source having an output at which appears a train of pulses, wherein said train constitutes alternate on-and-off periods of a signal; a pulse counter, and start/stop circuitry, said start/stop circuitry being actuable to a start condition and, alternately to a stop condition, said circuitry, upon actuation to said start condition, being responsive solely to an ending on-period of said signal to apply said signal, in its next following off-period, to said pulse counter; said pulse counter being responsive to said signal to count pulses in the form of on-periods of said signal applied thereto immediately following said off-period, said pulse counter being settable to produce a control signal upon counting an arbitrary predetermined number of the last said pulses; said start/stop circuitry being responsive to said control signal to prevent the on-period of signal next following the last of said predetermined number of pulses from being counted by said pulse counter; said programmed pulse switch being combined with pulse-actuated motive means of said control system for controlling a process with respect to a predetermined control point, said motive means being constructed and arranged for changing said control point in response to pulses of signal applied to said motive means, and in proportion to the number of said pulses applied to said motive means; said start/stop circuitry of said programmed pulse switch being arranged to apply the pulses applied to said pulse counter to said motive means, and to prevent pulses from being applied thereto when in its said stop condition; there being a pair of channels via which said pulses applied to said pulse counter are also applied to said mOtive means under control of said start/stop circuitry, and means for selecting one or the other only of said channels for applying the last said pulses to said motive means, said motive means being constructed and arranged to change said control point in a sense corresponding to the channel via which pulses are applied to said motive means.

Claim 16

A control system having a programmed pulse switch, said programmed pulse switch comprising a pulse source having an output at which appears a train of pulses, wherein said train constitutes alternate on-and-off periods of a signal; a pulse counter, and start/stop circuitry, said start/stop circuitry being actuable to a start condition and, alternately to a stop condition, said circuitry, upon actuation to said start condition, being responsive solely to an ending on-period of said signal to apply said signal, in its next following off-period, to said pulse counter; said pulse counter being responsive to said signal to count pulses in the form of on-periods of said signal applied thereto immediately following said off-period, said pulse counter being settable to produce a control signal upon counting an arbitrary predetermined number of the last said pulses; said start/stop circuitry being responsive to said control signal to prevent the on-period of signal next following the last of said predetermined number of pulses from being counted by said pulse counter; said programmed pulse switch being combined with pulse-actuated motive means of said control system for controlling a process with respect to a predetermined control point, said motive means being constructed and arranged for changing said control point in response to pulses of signal applied to said motive means, and in proportion to the number of said pulses applied to said motive means; said start/stop circuitry of said programmed pulse switch being arranged to apply the pulses applied to said pulse counter to said motive means, and to prevent pulses from being applied thereto when in its said stop condition; there being a pair of channels via which said pulses applied to said pulse counter are also applied to said mOtive means under control of said start/stop circuitry, and means for selecting one or the other only of said channels for applying the last said pulses to said motive means, said motive means being constructed and arranged to change said control point in a sense corresponding to the channel via which pulses are applied to said motive means.

Claim 17

The invention of claim 1, wherein one of said channels is arranged to cause the pulses applied via it to said motive means to have a sense opposite to the sense of pulses applied via the other of said channels to said motive means, whereby said motive means changes said control point in a sense corresponding to the pulses applied to said motive means.