Programmable sequential control means having a plurality of control circuits for controlling a respective plurality of discrete suboperations

Claim 2

A sequential operation control means having a plurality of control circuits of which each control circuit controls only a single discrete suboperation and said control circuits are activated successively and singly in a step-wise manner to deliver an order signal corresponding to the suboperation assigned thereto in response to receiving a sensor signal indicating a predetermined state of the subopeRation assigned to a preceding control circuit in the succession, further comprising: means for delivering concurrently with said order signal a set signal to the next control circuit in the succession; and a signal order discriminating subcircuit in each said control circuit responsive to the arrival of said set signal from a preceding control circuit and of said sensor signal from the suboperation being controlled by the said preceding control circuit, the latter control circuit being activated if, and only if, said set signal from said preceding control circuit is on before said sensor signal becomes concurrent therewith.

Claim 3

A sequential operation control means comprising: a plurality of control circuits, each of which controls only a single discrete suboperation and said control circuits are activated successively and singly in a step-wise manner to deliver an order signal corresponding to the suboperation assigned thereto, each control circuit including a logic section, a bistable memory section coupled to said logic section, an output section coupled to said memory section, said output section providing an order output signal and a step output signal in response to setting of said memory section, a first input and a second input connected to said logic section, a signal order discriminating circuit in said logic section responsive to the arrival of signals at both said first and said second logic circuit inputs for causing a set signal to be delivered from said logic section to said memory section if, and only if, the signal at said first logic circuit input is on before the signal at said second logic circuit input becomes concurrent therewith, and a third input coupled to said memory section for resetting said memory section; means for supplying an operation sensor signal; sensor signal program means coupled to said second input of said logic circuits and to said means for supplying said operation sensor signal, and including first means for selective interconnection thereof; step signal program means coupled to said first input of said logic circuits, to said third input and to said step signal outputs of said control circuits, and including second means for selective interconnection thereof; means for supplying an operation order signal; and output signal program means coupled to said order signal outputs of said control circuits, to said means for supplying said operation order signal, and including third means for selective interconnection thereof, to thereby control said suboperations.

Claim 4

A sequential operation control means comprising: a plurality of control circuits, each of which controls only a single discrete suboperation and said control circuits are activated successively and singly in a step-wise manner to deliver an order signal corresponding to the suboperation assigned thereto, each control circuit including a logic section, a bistable memory section coupled to said logic section, an output section coupled to said memory section, said output section providing an order output signal and a step output signal in response to setting of said memory section, a first input and a second input connected to said logic section, a signal order discriminating circuit in said logic section responsive to the arrival of signals at both said first and said second logic circuit inputs for causing a set signal to be delivered from said logic section to said memory section if, and only if, the signal at said first logic circuit input is on before the signal at said second logic circuit input becomes concurrent therewith, and a third input coupled to said memory section for resetting said memory section; means for supplying an operation sensor signal; sensor signal program means coupled to said second input of said logic circuits and to said means for supplying said operation sensor signal, and including first means for selective interconnection thereof; step signal program means coupled to said first input of said logic circuits, to said third input and to said step signal outputs of said control circuits, and including second means for selective interconnection thereof; means for supplying an operation order signal; and output signal program means coupled to said order signal outputs of said control circuits, to said means for supplying said operation order signal, and including third means for selective interconnection thereof, to thereby control said suboperations.

Claim 5

Control means according to claim 2, wherein each of said control circuits have similar logic and memory sections and are constructed as control unit modules (St; St1, St2, . . . ).

Claim 6

Control means according to claim 2, wherein said logic section and said memory section of a control circuit are comprised of fluidistor means, and wherein said logic section includes at least one active input which is activated by signals from said sensing means, and including means for selectively blocking air flow from said active input.

Claim 7

Control means according to claim 4, wherein said logic section contains first through fifth fluidistor means of the OR/NOR-type, at least the third through fifth fluidistor means having a first (a) and a second (b) input and all fluidistor means having a first (c) and a second (d) output, and wherein said memory section includes a sixth fluidistor means of a bistable type, the first fluidistor means of said logic section being arranged to invert input signals fed to the first input of the control circuit and arranged to control the first input of the fourth fluidistor means of said logic section by its first output (c1), which fourth fluidistor means via its second input (b4) is controlled by the first output (c3) of the third fluidistor means and which fourth fluidistor means via its first output (c4) is connected to the second input (b3) of the third fluidiStor means and via its second output (d4) to the first input (a5) of the fifth fluidistor means, a second fluidistor means being arranged to invert input signals fed to either an active or a passive second input of the control circuit and arranged to control by its first output (c2) the first input (a3) of the third fluidistor means and the second input (b5) of the fifth fluidistor means, whereby the third, fourth and fifth fluidistor means form said discriminating circuit for controlling the second input (b6) of the sixth fluidistor means of said memory section.

Claim 8

Control means according to claim 4, wherein said discriminating circuit in the logic section of said control circuit is comprised of a single fluidistor means, and including a positive feedback means for blocking holding except when the signal fed to said first logic circuit input occurs earlier than the input signal fed to said second logic circuit input.

Claim 9

Control means according to claim 2, wherein said control circuit is comprised of electrical elements.

Claim 10

Control means according to claim 7 wherein: said logic section of said control circuit comprises a first (16) and a second inverter (18) and a monostable multivibrator (19); said first inverter being arranged to be activated via the first input (i1) of the control circuit by means of a negative going signal or lack of signal and said monostable multivibrator (19) being arranged to be triggered via the second input (i2) of the control circuit by means of a positive going signal or by the presence of a signal from its stable state, which is the 0-state, into its 1-state; the output of the first inverter (16) being connected with the 1-output of the monostable multivibrator by means of which a logical AND-condition is achieved; and the second inverter (18) having its input connected to the interconnection point (17) between said multivibrator and said first inverter (16) and being arranged to control the memory section of said control circuit; said memory section comprises a bistable circuit having two NAND-gates (20, 21); and said output section comprises a monostable circuit (22) having a trigger input; one of the outputs of said memory section being connected to the trigger input of said monostable circuit (22) belonging to the output section for generating a pulsed output signal (u1''), and the second output of said memory section being connected directly to the step output (u2) of said output section, whereby pulsed or DC order signals my be selected by connecting either the pulsed output (u1'') or the step output (u2) to one or more activating means of the controlled process via said output signal program means.

Claim 11

Control means according to claim 8 wherein said output section includes an inverting buffer stage (23) and an inverting amplifier (24) coupled to at least one of the pulsed or step signal outputs.

Claim 12

Control means according to claim 7 wherein said logic section comprises a relay connected such that blocking against activation or blocking holding is obtained except when the signal fed to said first input occurs before the input signal fed to said second input.

Claim 13

Control means according to claim 10 wherein said three program means are combined to form a connecting terminal device for coupling the three programs, which terminal device is common to said programs and further serves as a support for program components and as a connecting device for connecting said program means with said control circuits.

Claim 14

Control means according to claim 2 wherein said logic section comprises a controllable, double throw, four-way valve having positive feedback such that it will be blocked against setting or will be held in its set condition for all conditions except when the input signal of said first input occurs earlier than the input signal of said second input.

Claim 15

Control means according to claim 2 wherein said progRam means comprise connecting terminal devices for coupling of programs, direct or indirect coupling of program signals to said control circuits, said control circuits and said program means forming a control unit.

Claim 16

Control means according to claim 2 comprising non-return valves connecting said step signal program means to respective step outputs.

Claim 17

Control means according to claim 2 comprising non-return valves connecting said step signal program means with respective first and third inputs of said control circuits.

Claim 18

Control means according to claim 2 wherein said step signal program means is provided with fixed signal connections according to a desired step sequence program.

Claim 19

Control means according to claim 2 comprising a bistable activating means coupling said control circuits to the suboperation means.

Claim 20

A sequential operation control means having a plurality of control circuits of which each circuit controls only a single discrete suboperation and said circuits are activated successively and singly in a step-wise manner to deliver an order signal to the suboperation assigned thereto in response to receiving a sensor signal indicating a predetermined state of the suboperation assigned to a preceding control circuit in the succession, further comprising: means for supplying operation sensor signals; means for supplying operation order signals; means in said control circuits for delivering concurrently with said order signal a set signal for the next control circuit in the succession; means in said control circuits for delivering concurrently with said order signal a reset signal for a preceding control circuit in the succession; a sensor signal program switchboard means connected to said control circuits and to said means for supplying operation sensor signals; means connectable to said sensor program switchboard means for permutating said sensor signals; an output signal program switchboard means connected to said order signal delivering means of said control circuit and to said means for supplying operation order signals; means connectable to said output signal program switchboard means for permutating said order signals; a set and reset signal program switchboard means connected to said control circuits; and means connectable to said set and reset signal switchboard means for permutating said set and reset signals.

Claim 21

A sequential operation control means having a plurality of control circuits of which each circuit controls only a single discrete suboperation and said circuits are activated successively and singly in a step-wise manner to deliver an order signal to the suboperation assigned thereto in response to receiving a sensor signal indicating a predetermined state of the suboperation assigned to a preceding control circuit in the succession, further comprising: means for supplying operation sensor signals; means for supplying operation order signals; means in said control circuits for delivering concurrently with said order signal a set signal for the next control circuit in the succession; means in said control circuits for delivering concurrently with said order signal a reset signal for a preceding control circuit in the succession; a sensor signal program switchboard means connected to said control circuits and to said means for supplying operation sensor signals; means connectable to said sensor program switchboard means for permutating said sensor signals; an output signal program switchboard means connected to said order signal delivering means of said control circuit and to said means for supplying operation order signals; means connectable to said output signal program switchboard means for permutating said order signals; a set and reset signal program switchboard means connected to said control circuits; and means connectable to said set and reset signal switchboard means for permutating said set and reset signals.

Claim 22

A sequential operation control means according to claim 18 wherein said control circuits each include a logic section, a memory section coupled to said logic section, an output section coupled to said memory section, said output section providing respectively an order output signal, a set output signal, and a reset output signal, first and second inputs connected to said logic section for receiving respectively a set and a sensor signal, and a signal order discriminating circuit in said logic section responsive to the arrival of signals at both said first and second logic circuit inputs for causing said order, set, and reset signals to be delivered if, and only if, the signal at said first logic circuit input arrives before the signal at said second logic circuit input.