US3553489A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Phase sequence comparator
Assignee: English Electric Co Ltd
•
Filing: 1967-12-18
•
Granted: 1971-01-05
•
Expires: 1987-12-18
Abstract
Abstract This invention relates to a comparator for sensing the sequence of four input signals A,B,C,D applied thereto in succession. In its basic concept the comparator comprises two bistable devices each having a first input connected in common to receive the signal A from one input stage and the signal D from another input stage. One of the devices has a second input for receiving the signal B and the other device has a second input for receiving the signal C. With this circuit arrangement a coincident change of state occurs in both of the devices upon the occurrence of the signal D provided that the inputs to the one device are in the sequence A, B,D, and the inputs to the other device are in the sequence ACD. The outputs from these two devices are applied to an AND gate together with the pulse D whereby a coincidence of all three inputs to this gate is indicative of the input signals occurring in the sequence ABCD or ACBD.
Inventors
- 👤 Derek John Spencer
- 👤 Eric Paddison
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 18:19
CPC Classifications
H; H02; H02H; H02H11/00; H02H11/004; G; G01; G01R; G01R29/00; G01R29/18; H02H3/00; H02H3/38; H02H3/382; H03; H03K; H03K5/00; H03K5/22; H03K5/26
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
87 words
A circuit for determining whether all of a plurality of phase signals on separate lines appear between two reference signals, comprising a respective bistable circuit for each phase signal which is set to the same state by both the reference signals and to the opposite state by the respective phase signal, and gating means fed from all the bistable devices and with the second reference signal and effective to produce an output only when the second reference signal appears and all the bistable circuits change state together.
Claim 2
Dependent Claim
87 words
A circuit for determining whether all of a plurality of phase signals on separate lines appear between two reference signals, comprising a respective bistable circuit for each phase signal which is set to the same state by both the reference signals and to the opposite state by the respective phase signal, and gating means fed from all the bistable devices and with the second reference signal and effective to produce an output only when the second reference signal appears and all the bistable circuits change state together.
Claim 3
Dependent Claim
67 words
A circuit according to claim 1, wherein the input signals are in the form of pulses derived from different sinusoidal input quantities at predetermined instants during their cycles, the polarity of the pulses being in accord with the direction of the signal transition at said instants and each bistable circuit being set to one or the other state depending on the polarity of the pulse setting it.
Claim 4
Dependent Claim
73 words
A circuit according to claim 2, wherein the gating means comprises two parallel strings of transistors, having collector, base and emitter electrodes, the transistors in each string having series-connected collector-emitter paths, a common load resistor for said transistors, and a plurality of commonly center tapped windings respectively coupled to receive the outputs from the bistable devices and the second reference signal, the base electrodes of corresponding transistors being connected together through these windings.
Claim 5
Dependent Claim
87 words
A circuit according to claim 2, wherein the gating means comprises two AND gates, each gate having a plurality of inputs respectively connected to the corresponding outputs from all the bistable devices and a further input for receiving the second reference signal, an output being developed from one of the AND gates in response to coincident pulses of one polarity at all its inputs and an output being developed from the other AND gate in response to coincident pulses of the opposite polarity at all its inputs.
Claim 6
Dependent Claim
45 words
A circuit according to claim 4, wherein the two AND gates feed respective pulse stretcher circuits which extend the pulse length over a duration equal to at least the interval between successive reference signals, and a further AND gate fed from the pulse stretcher circuits.
Claim 7
Dependent Claim
13 words
A circuit according to claim 5, wherein the bistable devices are magnetic cores.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-01-04 | 1974-07-06 | 1975-01-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-01-04 | 1978-07-06 | 1979-01-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-01-04 | 1982-07-06 | 1983-01-05 | $7700.00 | Window Closed / Lapsed |