US3848141A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor delay lines using three terminal transferred electron devices
Assignee: RCA Corp
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Filing: 1973-03-26
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Granted: 1974-11-12
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Expires: 1993-03-26
Abstract
Abstract Presented is a semiconductor delay line which makes use of the transferred electron effect in order to provide useful delays in information processing applications at multigigabit rates.
Inventors
- 👤 F Sterzer
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 16:49
CPC Classifications
H; H03; H03H; H03H11/00; H03H11/02; H03H11/26; H03H11/265
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
185 words
A semiconductor delay line comprisIng: a. a first transferred electron device having input, output and third terminals, said device generating an output signal in response to a predetermined D.C. bias voltage coupled to said first device third terminal and an input signal having a predetermined waveform coupled to said first device input terminal, said first device output signal having a nonuniform current characteristic; b. an active element having input and output terminals; c. means for biasing said transferred electron device at a voltage above its domain sustaining voltage and below its threshold voltage; d. means for biasing said active element below its triggering threshold; and e. means for coupling said first device output signal from said first device output terminal to said input terminal of said active element whereby said active element will be triggered by said transferred electron device into generating an active element output electrical signal having said input signal waveform following a delay determined by said nonuniform current characteristic of said transferred electron device output signal, said biasing means for said transferred electron device and said threshold level of said active element.
Claim 2
Dependent Claim
185 words
A semiconductor delay line comprisIng: a. a first transferred electron device having input, output and third terminals, said device generating an output signal in response to a predetermined D.C. bias voltage coupled to said first device third terminal and an input signal having a predetermined waveform coupled to said first device input terminal, said first device output signal having a nonuniform current characteristic; b. an active element having input and output terminals; c. means for biasing said transferred electron device at a voltage above its domain sustaining voltage and below its threshold voltage; d. means for biasing said active element below its triggering threshold; and e. means for coupling said first device output signal from said first device output terminal to said input terminal of said active element whereby said active element will be triggered by said transferred electron device into generating an active element output electrical signal having said input signal waveform following a delay determined by said nonuniform current characteristic of said transferred electron device output signal, said biasing means for said transferred electron device and said threshold level of said active element.
Claim 3
Dependent Claim
53 words
The semiconductor delay line of claim 1 wherein said active element comprises a second transferred electron device having input, output and third terminals, said second device input terminal being coupled to said first device output terminal and means for biasing said second device above its domain sustaining voltage and below its threshold voltage.
Claim 4
Dependent Claim
49 words
The semiconductor delay line of claim 1 wherein said means for biasing said first transferred electron device comprises a DC biasing source having a positive terminal connected to said third terminal of said first device and a resistor serially connected between said first device output terminal and reference potential.
Claim 5
Dependent Claim
49 words
The semiconductor delay line of claim 2 wherein said means for biasing said second transferred electron device comprises a DC biasing source having a positive terminal connected to said third terminal of said second device and a resistor serially connected between said second device output terminal and reference potential.
Claim 6
Dependent Claim
51 words
The semiconductor delay line of claim 2 wherein said means for coupling said first device output signal to said input terminal of said second transferred electron device comprises an electrical connection between said output terminal of said first transferred electron device and said input terminal of said second transferred electron device.
Claim 7
Dependent Claim
20 words
The semiconductor delay line of claim 2 wherein said second transferred electron device output signal has a uniform current characteristic.
Claim 8
Dependent Claim
20 words
The semiconductor delay line of claim 2 wherein said second transferred electron device output signal has a nonuniform current characteristic.
Claim 9
Dependent Claim
103 words
The semiconductor delay line of claim 7 further comprising at least one additional transferred electron device having input, output and third terminals, said device generating an output signal having a nonuniform current characteristic, in response to a predetermined DC bias voltage coupled to said third terminal and said output signal from said second transferred electron device coupled to said additional transferred electron device input terminal, and said additional device having a resistor serially connected between said additional device output terminal and reference potential for biasing said additional transferred electron device at a point above its domain sustaining voltage and below its threshold voltage.
Claim 10
Dependent Claim
104 words
The semiconductor delay line of claim 8 further comprising a terminating transferred electron device having input, output and third terminals, said terminating device generating an output signal having a uniform current characteristic in response to a predetermined DC bias voltage coupled to said third terminal and said output signal from said additional transferred electron device coupled to saiD terminating transferred electron device input terminal, said terminating transferred electron device having a resistor serially connected between said terminating device output terminal and said reference potential for biasing said terminating transferred electron device at a point above its domain sustaining voltage and below its threshold voltage.
Claim 11
Dependent Claim
19 words
The semiconductor delay line of claim 1 further comprising means for adjusting said threshold level of said active element.
Claim 12
Dependent Claim
32 words
The semiconductor delay line of claim 10 wherein said nonuniform current characteristic of said first transferred electron device monotonically decreases after a domain has been nucleated within said first transferred electron device.
Claim 13
Dependent Claim
27 words
The semiconductor delay line of claim 10 wherein said coupling means comprises a circuit of the type which will segregate direct current while passing alternating current signals.
Claim 14
Dependent Claim
49 words
The semiconductor delay line of claim 11 wherein said means for adjusting said threshold level comprises an adjustable DC biasing source, said DC biasing source being AC isolated from said output terminal of said first transferred electron device and from said input terminal of said second transferred electron device.
Claim 15
Dependent Claim
42 words
The semiconductor delay line of claim 11 wherein said coupling means comprises a capacitor having one terminal connected to said output terminal of said first transferred electron device and having the other terminal connected to said input terminal of said active element.
Claim 16
Dependent Claim
128 words
A semiconductor delay line comprising a plurality of delay units cascaded in series, each delay unit comprising: a. a transferred electron device having anode, cathode and gate terminals, said device generating an output signal in response to a predetermined DC bias voltage coupled to said anode terminal and an input signal coupled to said gate terminal, said output signal having a nonuniform current characteristic; b. a biasing resistor connected between said cathode of said transferred electron device and a ground terminal; c. an input terminal connected to said gate terminal of said transferred electron device; d. an output terminal connected to said cathode terminal of said transferred electron device; and e. a bias supply connected between said anode terminal of said transferred electron device and said ground terminal.
Claim 17
Dependent Claim
128 words
A semiconductor delay line comprising a plurality of delay units cascaded in series, each delay unit comprising: a. a transferred electron device having anode, cathode and gate terminals, said device generating an output signal in response to a predetermined DC bias voltage coupled to said anode terminal and an input signal coupled to said gate terminal, said output signal having a nonuniform current characteristic; b. a biasing resistor connected between said cathode of said transferred electron device and a ground terminal; c. an input terminal connected to said gate terminal of said transferred electron device; d. an output terminal connected to said cathode terminal of said transferred electron device; and e. a bias supply connected between said anode terminal of said transferred electron device and said ground terminal.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-11-11 | 1978-05-13 | 1978-11-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-11-11 | 1982-05-13 | 1982-11-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-11-11 | 1986-05-13 | 1986-11-12 | $7700.00 | Window Closed / Lapsed |