Method and means for resetting filament-forming memory semiconductor device

Claim 3

The method of claim 1 wherein said memory semi-conductor material has the general formula: GeATeBXCYD where: A 5 to 60 atomic percent B 30 to 95 atomic percent C 0 to 10 atomic percent when x is Antimony (Sb) or Bismuth (Bi) or C 0 to 40 atomic percent when x is Arsenic (As) D 0 to 10 atomic percent when y is Sulphur (S) or D 0 to 20 atomic percent when y is Selenium (Sc).

Claim 4

The method of claim 1 wherein each of said reset current pulses is of a magnitude to heat substantially the entire filament above the glass transition temperature thereof.

Claim 5

In combination, a filament-type memory device including spaced electrodes between which extend a body of generally amorphous substantially non-conductive memory semiconductor material which, when a set voltage pulse in excess of a given threshold voltage value and duration is applied to said electrodes has formed therein, a crystalline low resistance filamentous path resettable into a generally amorphous condition by application of one or more reset voltage pulses producing reset current pulses through said filamentous path which heat the same to a temperature which dissipates the crystalline filament and are of a duration which is so short that upon termination of each reset current pulse the filamentous path will be quickly quenched to leave at least portions of the filamentous path in a substantially amorphous condition; and a source of reset voltage pulses selectively connectable to said electrodes for applying an initial set voltage pulse or pulses which produces a reset current pulse or pulses which substantially completely convert the crystalline filamentous path to a substantially amorphous filamentous path where the memory device has its maximum resistance and threshold voltage value and subsequent reset voltage pulses each in excess of the maximum threshold voltage value of the memory device which additional voltage Pulses cause additional reset current pulses to flow through the high resistance filamentous path to homogenize the same and prevent crystallization from developing therein due to high ambient temperature storage of the memory device.

Claim 6

In combination, a filament-type memory device including spaced electrodes between which extend a body of generally amorphous substantially non-conductive memory semiconductor material which, when a set voltage pulse in excess of a given threshold voltage value and duration is applied to said electrodes has formed therein, a crystalline low resistance filamentous path resettable into a generally amorphous condition by application of one or more reset voltage pulses producing reset current pulses through said filamentous path which heat the same to a temperature which dissipates the crystalline filament and are of a duration which is so short that upon termination of each reset current pulse the filamentous path will be quickly quenched to leave at least portions of the filamentous path in a substantially amorphous condition; and a source of reset voltage pulses selectively connectable to said electrodes for applying an initial set voltage pulse or pulses which produces a reset current pulse or pulses which substantially completely convert the crystalline filamentous path to a substantially amorphous filamentous path where the memory device has its maximum resistance and threshold voltage value and subsequent reset voltage pulses each in excess of the maximum threshold voltage value of the memory device which additional voltage Pulses cause additional reset current pulses to flow through the high resistance filamentous path to homogenize the same and prevent crystallization from developing therein due to high ambient temperature storage of the memory device.

Claim 7

The combination of claim 4 wherein said source of reset voltage pulses is a constant current source which automatically produces a sufficient output voltage to produce constant amplitude reset current pulses independently of the impedance value of the memory device.

Claim 8

The combination of claim 5 wherein said memory semiconductor material has the general formula: GeATeBXCYD where: A 5 to 60 atomic percent B 30 to 95 atomic percent C 0 to 10 atomic percent when x is Antimony (Sb) or Bismuth (Bi) or C 0 to 40 atomic percent when x is Arsenic (As) D 0 to 10 atomic percent when y is Sulphur (S) or D 0 to 20 atomic percent when y is Selenium (Se).

Claim 9

In combination, a memory device which includes a pair of spaced electrodes between which extends a body of generally amorphous substantially non-conductive memory semi-conductor material made of a composition of at least two elements, said composition when a set voltage pulse in excess of a given threshold voltage value is applied to said electrodes for a given period becoming conductive as current flows through a filamentous path therein, termination of said set voltage pulse leaving said filamentous path as a crystalline relatively low resistance deposit of at least one of said elements, and after one or a few current reset pulses of a given amplitude and duration much less than said given period are fed through said filamentous path, said path is in a substantially amorphous condition where the memory device has its maximum resistance and threshold voltage value, said reset filamentous path being a non-homogeneous composition of said elements with various regions thereof containing greater concentrations of said elements in the amorphous state than other regions thereof; and a reset circuit for said memory device for selectively applying across said spaced electrodes during each reset operation a plurality of reset voltage pulses, the initial pulse or pulses of which leave said path in said substantially amorphous condition where the device has said maximum resistance and threshold voltage value and at least the subsequent reset voltage pulses of which exceed said maximum threshold value to cause additional reset current pulses to flow in said filamentous path, which homogenize said non-homogeneous regions of said filamentous path.

Claim 10

In combination, a memory device which includes a pair of spaced electrodes between which extends a body of generally amorphous substantially non-conductive memory semi-conductor material made of a composition of at least two elements, said composition when a set voltage pulse in excess of a given threshold voltage value is applied to said electrodes for a given period becoming conductive as current flows through a filamentous path therein, termination of said set voltage pulse leaving said filamentous path as a crystalline relatively low resistance deposit of at least one of said elements, and after one or a few current reset pulses of a given amplitude and duration much less than said given period are fed through said filamentous path, said path is in a substantially amorphous condition where the memory device has its maximum resistance and threshold voltage value, said reset filamentous path being a non-homogeneous composition of said elements with various regions thereof containing greater concentrations of said elements in the amorphous state than other regions thereof; and a reset circuit for said memory device for selectively applying across said spaced electrodes during each reset operation a plurality of reset voltage pulses, the initial pulse or pulses of which leave said path in said substantially amorphous condition where the device has said maximum resistance and threshold voltage value and at least the subsequent reset voltage pulses of which exceed said maximum threshold value to cause additional reset current pulses to flow in said filamentous path, which homogenize said non-homogeneous regions of said filamentous path.

Claim 11

The combination of claim 7 wherein said at least one element of the memory semiconductor material of said memory device has a crystallization temperature at or below 70*C, and the crystallization temperature of said composition of amorphous semiconductor material is greatly in excess of 70*C.

Claim 12

The combination of claim 8 wherein said memory semiconductor material has the formula: GeATeBXCYD where: A 5 to 60 atomic percent B 30 to 95 atomic percent C 0 to 10 atomic percent when x is antimony (Sb) or Bismuth (Bi) or C 0 to 40 atomic percent when X is Arsenic (As) D 0 to 10 atomic percent when Y is Sulphur (S) or D 0 to 20 atomic percent when Y is Selenium (Se).