Current attenuator

Claim 2

A current attenuator comprising: a first terminal and a second terminal between which an input current may be applied; a transistor having a base electrode and an emitter electrode and a base-emitter semiconductor junction therebetween and having a collector electrode; a first number M of semiconductor junctions serially connected from said transistor base electrode to said first terminal; a second number N of semiconductor junctions serially connected from said transistor emitter electrode, to said first terminal, one of the numbers M and N being one more than the other, each said semiconductor junction in the larger of said first and said second numbers having a higher conductivity on average than the conductivity on average of each semiconductor junction in the smaller of said first and said second numbers; means responding to said input current flow between said first and said second terminals and splitting it into two portions, namely, first and second currents, each in fixed proportion to the other, said first current being applied between said base electrode and said first terminal and said second current being applied between said emitter electrode and said first terminal; and a third terminal to which said transistor collector electrode is connected for supplying an output current substantially smaller than said first and said second currents.

Claim 3

A current attenuator as claimed in claim 1 wherein said means responding to said input current flow between said first and said second terminals and splitting it into two portions comprises: a third number M of semiconductor junctions serially connected from said second terminal to said transistor emitter electrode and a fourth number N of semiconductor junctions serially connected from said second terminal to said transistor base electrode, each said semiconductor junction in the larger of said third and said fourth numbers having a higher conductivity on average than each said semiconductor junction in the smaller of said third and said fourth numbers.

Claim 4

A current atTenuator as claimed in claim 1 wherein said means responding to said input current flow between said first and said second terminals and splitting it into two portions includes: a three-terminal current amplifier having an input terminal and an output terminal connected to separate ones of the base and the emitter electrodes of said first transistor and having a common terminal connected to said second terminal.

Claim 5

A current attenuator comprising: first, a second and third terminals; first and second and third and fourth and fifth and sixth and seventh transistors, each having a base and an emitter and a collector electrode, each having a base-emitter junction between its said base and emitter electrodes and a collector-to-emitter path between its collector and emitter electrodes, said first and said second and said third and said fourth transistors being matched to each other, said fifth and said sixth transistors being matched to each other, said first transistor emitter electrode and said second transistor collector electrode being connected, said third transistor emitter electrode and said fourth transistor collector electrode being connected, said second and said third and said fifth and said sixth transistors each having its base electrode connected to its collector electrode, said fifth transistor collector-to-emitter path being connected between the collector and base electrodes of said first transistor, said sixth transistor collector-to-emitter path being connected between the collector and base electrodes of said fourth transistor, the collector electrodes of said first and said third transistors being connected to said first terminal, the emitter electrodes of said second and said fourth transistors being connected to said second terminal, the collector electrode of said seventh transistor being connected to said third terminal, and said seventh transistor base emitter junction being connected between the emitter electrodes of said first and said third transistors.

Claim 6

A current attenuator comprising: first, a second and third terminals; first and second and third and fourth and fifth and sixth and seventh transistors, each having a base and an emitter and a collector electrode, each having a base-emitter junction between its said base and emitter electrodes and a collector-to-emitter path between its collector and emitter electrodes, said first and said second and said third and said fourth transistors being matched to each other, said fifth and said sixth transistors being matched to each other, said first transistor emitter electrode and said second transistor collector electrode being connected, said third transistor emitter electrode and said fourth transistor collector electrode being connected, said second and said third and said fifth and said sixth transistors each having its base electrode connected to its collector electrode, said fifth transistor collector-to-emitter path being connected between the collector and base electrodes of said first transistor, said sixth transistor collector-to-emitter path being connected between the collector and base electrodes of said fourth transistor, the collector electrodes of said first and said third transistors being connected to said first terminal, the emitter electrodes of said second and said fourth transistors being connected to said second terminal, the collector electrode of said seventh transistor being connected to said third terminal, and said seventh transistor base emitter junction being connected between the emitter electrodes of said first and said third transistors.

Claim 7

A current attenuator as claimed in claim 4 wherein: said first, said second, said third, said fourth, said fifth, said sixth and said seventh transistors are all of the same conductivity type.

Claim 8

A current attenuator as claimed in claim 4 wherein: said fifth, said sixth and said seventh transistors are of the same conductivity type to each other and of complementary conductivity type to said first, said second, said third and said fourth transistors.

Claim 9

In combination: first, second, third, and fourth terminals; first and second pluralities of semiconductor junctions, said first and said second pluralities being of equal number to each other and each consisting of a first and a second portion, each semiconductor junction in said first portion of said first and said second pluralities having a higher conductivity on average than the conductivity on average of each semiconductor junction in its respective second portion; means arranging the semiconductor junctions in said first plurality in a first serial combination such that said first portion thereof connects said first and said second terminals and that said second portion thereof connects said second and third terminals, and means arranging the semiconductor junctions in said second plurality in a second serial combination, such that said first portion thereof connects said fourth and said third terminals, that said second portion thereof connects said first and said fourth terminals and that said first and said second serial combination are in parallel combination with each other for current as may be applied between said first and said third terminals.

Claim 10

In combination: first, second, third, and fourth terminals; first and second pluralities of semiconductor junctions, said first and said second pluralities being of equal number to each other and each consisting of a first and a second portion, each semiconductor junction in said first portion of said first and said second pluralities having a higher conductivity on average than the conductivity on average of each semiconductor junction in its respective second portion; means arranging the semiconductor junctions in said first plurality in a first serial combination such that said first portion thereof connects said first and said second terminals and that said second portion thereof connects said second and third terminals, and means arranging the semiconductor junctions in said second plurality in a second serial combination, such that said first portion thereof connects said fourth and said third terminals, that said second portion thereof connects said first and said fourth terminals and that said first and said second serial combination are in parallel combination with each other for current as may be applied between said first and said third terminals.

Claim 11

A combination as claimed in claim 7 including: a fifth terminal and a junction transistor having base and emitter electrodes connected to said second terminal and to said fourth terminal respectively and having a collector electrode connected to said fifth terminal.

Claim 12

An unbalanced bridge consisting solely Of semiconductor junctions comprising in combination: first and second input terminals between which an input current may be applied; third and fourth terminals serving as output terminals; first and second bridge arms respectively comprising M and N series connected semiconductor junctions, said first arm connected between the first and third terminals and said second arm connected between the third and second terminals; a third bridge arm comprising M series connected semiconductor junctions, each junction area p, said third arm connected between said fourth and second terminals; and a fourth bridge arm comprising N series connected semiconductor junctions, each junction of area q, said fourth arm connected between said first and fourth terminals, where M and N are integers, where p differs substantially from q and where all junctions are connected in the forward direction with respect to the flow of said input current.

Claim 13

An unbalanced bridge consisting solely Of semiconductor junctions comprising in combination: first and second input terminals between which an input current may be applied; third and fourth terminals serving as output terminals; first and second bridge arms respectively comprising M and N series connected semiconductor junctions, said first arm connected between the first and third terminals and said second arm connected between the third and second terminals; a third bridge arm comprising M series connected semiconductor junctions, each junction area p, said third arm connected between said fourth and second terminals; and a fourth bridge arm comprising N series connected semiconductor junctions, each junction of area q, said fourth arm connected between said first and fourth terminals, where M and N are integers, where p differs substantially from q and where all junctions are connected in the forward direction with respect to the flow of said input current.

Claim 14

An unbalanced bridge as set forth in claim 9, further including means responsive to the potential developed between said third and fourth terminals in response to input current flow between said first and second terminals, for producing an output current substantially smaller in value than said input current.

Claim 15

An unbalanced bridge as set forth in claim 10, wherein said means comprises a transistor having an emitter-base junction and a collector electrode, said emitter-base junction coupled, in the forward direction, between said third and fourth terminals, and a terminal coupled to said collector electrode to which a current may be applied.

Claim 16

An unbalanced bridge as set forth in claim 9, wherein the M series connected semiconductor junctions in said first bridge arm are each of area q and the N series connected semiconductor junctions in said second bridge arm are each of area p.

Claim 17

An unbalanced bridge as set forth in claim 9, wherein M and N are different integers.

Claim 18

An unbalanced bridge as set forth in claim 13, wherein N equals M + 1 and a transistor has a base electrode directly connected to said third terminal, and has an emitter electrode directly connected to said fourth terminal and has a collector electrode connected so one output current responsive to said input current can flow therethrough.

Claim 19

An unbalanced bridge as set forth in claim 9, wherein each semiconductor junction comprises a transistor connected to operate as a diode.