Delayless transistor latch circuit

Claim 1

A semiconductor circuit for providing a latched output signal without introducing circuit delay due to the latching function comprising: an input node; an intermediate node; an output node; a field effect transistor having a gating electrode and two gated electrodes, the first of said gated electrodes being operatively connected to a first fixed potential level, the second of said gated electrodes being operatively connected to said intermediate node, said gating electrode being operatively connected to said input node; a plurality of parallel connected field effect transistor gates each having two gated electrodes and a gating electrode, one of said plurality of field effect transistors having its gating electrode operatively connected to said intermediate node, the first each of the gated electrodes of said plurality being operatively connected to said output node, the second of the gated electrodes of said plurality being operatively connected to a second fixed potential level; and latching means operatively connected to said to said intermediate node, responsive to and holding the signal on said intermediate node, thereby latching the signal at said output node, said latching means having a pair of cross-coupled field effect transistors, a pair of load field effect transistors, each operatively associated with one of said cross-coupled field effect transistors having a gating electrode operatively connected to said intermediate node, isolation means operatively connected in a series path between said gating electrode and a gated electrode of the other one of said crosscoupled field effect transistors; and reset means operatively connected between the intermediate node and said second fixed potential level.