US3845475A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Sequential data transmission system with insertion of slow-sequence operations
Assignee: Jeumont Schneider SA
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Filing: 1973-06-11
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Granted: 1974-10-29
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Expires: 1993-06-11
Abstract
Abstract A sequential data transmission system such that an instruction for slow-sequence operations being inserted into a program of fast-sequence operations controlled by a pulse counter. The same is controlled by a clock and associated with sequence switch. The system is characterized in that when a slow sequence is triggered, the counter produces the zero state at the output of a first logic operator connected to the input of a pulse-shaping circuit whose output is connected to the first input of a second logic operator, the same having two inputs. The second input of the second logic operator is connected to a normally open relay contact which closes upon termination of the slow-sequence operation. The output of the second logic operator is connected to an input of a bistable and causes the output thereof to take up a fixed logic state if the pulse-shaping circuit is operative and if the relay contact is open. This fixed logic state blocks the pulse counter by way of a third logic operator; and the bistable positioned in accordance with the foregoing is reset by a signal which is synchronous with but offset from the clock signal.
Inventors
- 👤 J Massaloux
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 16:01
CPC Classifications
G; G06; G06F; G06F3/00; G06F1/00; G06F1/04
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
222 words
In an assembly comprisinG a plurality of subassemblies, apparatus for inhibiting control pulses controlling fast sequence operations of relatively fast sub-assemblies to permit slow sequence operations for relatively slow sub-assemblies comprising: a. clock means for providing clock pulses, b. pulse counter means connected to receive said clock pulses and to provide said control pulses, c. switching means connected to receive said control pulses and to provide a switching output signal associated with a first relatively slow sub-assembly, d. logic means connected to receive said switching output signal and connected to inhibit said control pulses from said pulse counter means by providing a counter inhibit signal, e. said logic means comprising: a first timing circuit responsive to said switching output signal and said control pulses, said timing circuit providing a timed inhibit signal, said time inhibit signal terminating after a fixed time, relay means controlled by said first relatively slow subassembly for providing a relay signal upon completion of said slow sequence of operations associated with said first relatively slow sub-assembly, and first gate means connected to receive said timed inhibit signal and said relay signal, said first gate means providing said counter inhibit signal to said pulse counter means in response to said timed inhibit signal, and said first gate means terminating said counter inhibit signal in response to said relay signal.
Claim 2
Dependent Claim
222 words
In an assembly comprisinG a plurality of subassemblies, apparatus for inhibiting control pulses controlling fast sequence operations of relatively fast sub-assemblies to permit slow sequence operations for relatively slow sub-assemblies comprising: a. clock means for providing clock pulses, b. pulse counter means connected to receive said clock pulses and to provide said control pulses, c. switching means connected to receive said control pulses and to provide a switching output signal associated with a first relatively slow sub-assembly, d. logic means connected to receive said switching output signal and connected to inhibit said control pulses from said pulse counter means by providing a counter inhibit signal, e. said logic means comprising: a first timing circuit responsive to said switching output signal and said control pulses, said timing circuit providing a timed inhibit signal, said time inhibit signal terminating after a fixed time, relay means controlled by said first relatively slow subassembly for providing a relay signal upon completion of said slow sequence of operations associated with said first relatively slow sub-assembly, and first gate means connected to receive said timed inhibit signal and said relay signal, said first gate means providing said counter inhibit signal to said pulse counter means in response to said timed inhibit signal, and said first gate means terminating said counter inhibit signal in response to said relay signal.
Claim 3
Dependent Claim
14 words
Apparatus as recited in claim 1 wherein said timing circuit comprises a monostable multivibrator.
Claim 4
Dependent Claim
29 words
Apparatus as recited in claim 1 further comprising a timing circuit, associated relay means and associated first gate means for each of a plurality of separate relatively slow sub-assemblies.
Claim 5
Dependent Claim
15 words
Apparatus as recited in claim 1 wherein said relay means comprises a normally open relay.
Claim 6
Dependent Claim
49 words
Apparatus as recited in claim 1 further comprising: a. second gate means connected between said clock means and said pulse counter means, and b. bistable circuit means having one input connected to said first gate means, said bistable circuit means having an output connected to said second gate means.
Claim 7
Dependent Claim
54 words
Apparatus as recited in claim 6 further comprising a timing circuit, associated relay means and associated first gate means for each of a plurality of separate relatively slow sub-assemblies and wherein the first gate means corresponding to each of said relatively slow sub-assemblies is connected to said one input of said second gate means.
Claim 8
Dependent Claim
25 words
Apparatus as recited in claim 6 wherein said clock means provides a series of second clock pulses to a second input of said bistable circuit.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-10-28 | 1978-04-29 | 1978-10-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-10-28 | 1982-04-29 | 1982-10-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-10-28 | 1986-04-29 | 1986-10-29 | $7700.00 | Window Closed / Lapsed |