Analog-digital converter of the re-circulation type

Claim 2

A convertor according to claim 1, wherein said first threshold comparator means includes a first output bistable flip-flop and said second threshold comparator means includes a second output bistable flip-flop, the output of said first or second bistable flip-flops being connected to an input of a third bistable flip-flop providing an output indicative of the sign of the level to be coded, starting from the first time the threshold is exceeded.

Claim 3

A convertor according to claim 3, further comprising two current injectors having high internal resistance, one for each polarity level to be coded, each of said current injectors being responsive to an output of one of said first and second bistable flip-flops for passing a calibrated current to said amplifier via an input resistor having a much lower ohmic value than the internal resistance of said current injectors.

Claim 4

A convertor according to claim 4, wherein the level to be coded is applied to an input terminal of said amplifier via current weakening means having a ratio of 1:2 connected in series with a first analog gate connected to said input terminal of said amplifier.

Claim 5

A convertor according to claim 5, further comprising second, third, fourth and fifth analog gates, said amplifier having the input thereof connected to said third and fifth gates and the output thereof connected to said second and fourth gates, said second and third gates having a common junction point and a first capacitor being connected to said common junction point of said second and third gates, said fourth and fifth gates having a common junction point and a second capacitor being connected to said common junction point of said fourth and fifth gates, and logic means for establishing conductive paths at successive clock instants for rendering only the first and second gates conductive at the first clock instant and for alternately rendering only the third and fourth gates and then only the second and fifth gates conductive in accordance with succeeding clock instants.

Claim 6

A convertor according to claim 6, wherein said logic switching means includes first logic means for blocking the input of the counter at the first clock instant corresponding to the first time the threshold is exceeded and second logic means for opening the access of the shift register means for a predetermined number of clock instants.

Claim 7

A convertor according to claim 7, wherein said shift register means is opened for access for four clock instants for four bits.

Claim 8

A convertor according to claim 7, wherein said logic switching means includes blocking logic means for blocking said counter means at a predetermined clock instant if said counter means has not been previously blocked.

Claim 9

An analog-to-digital convertor of the re-circulating type for compression law coding having a codIng characteristic formed by n sections whose successive slopes decrease according to binary law, comprising clock means for supplying clock pulses, a plurality of amplifier-comparator stages, each of said amplifier-comparator stages having an amplifier having a gain of two for amplifying a level to be coded applied to the input of the amplifier, the amplifiers of the plurality of stages being connected in series such that the output of the amplifier of the preceding stage is applied to the input of the amplifier of the succeeding stage, each of the stages including a first threshold comparator means connected to the output of the amplifier of the respective stage for comparing amplified positive levels to be coded with a predetermined threshold and providing an output indicative thereof, second threshold comparator means connected to the output of the amplifier of the respective stage for comparing amplified negative levels to be coded with a predetermined threshold and providing an output indicative thereof, the first and second threshold comparator means of each stage having an operating rhythm controlled by the clock pulses, the convertor further including counter means for counting clock pulses starting with an original pulse, shift register means, and logic switching means for controlling the application of clock pulses to the counter means and to the shift register means, the logic switching means being responsive to an output of the first or second threshold comparator means from one of the stages indicating that a threshold has been exceeded for a first time for blocking the counting of pulses by the counter means and for enabling the application of clock pulses to the shift register means, wherein the complete coding is formed by a first series of bits supplied by the counter means indicating the order of the section of the coding characteristic and a second series of bits supplied by the shift register means indicating the position of the level of the section.

Claim 10

A convertor according to claim 10, wherein each comparator means of each stage is provided with an output bistable flip-flop, and each stage further includes two current injectors having high internal resistance, one for each polarity level to be coded, each of the current injectors being arranged for passing a calibrated current to the amplifier of the respective stage via an input resistor having a much lower ohmic value than the internal resistance of the current injectors, the current injectors of the second stage being controlled by the bistable flip-flops of the first stage and the current injectors of the next succeeding stage being controlled by the bistable flip-flops of the previous stage with the current injectors of the first stage being controlled by the bistable flip-flops of the last stage.

Claim 11

A convertor according to claim 11, wherein an input level to be coded is applied to an input terminal of the amplifer of the first stage via current weakening means having a ratio of 1:2 connected in series with a first analog gate connected to the input terminal of the amplifier.

Claim 12

A convertor according to claim 12, further comprising second, third, fourth and fifth analog gates, the amplifier of the first stage having the input thereof connected to the third and fifth gates and the amplifier of the last stage having the output thereof connected to the second and fourth gates, the second and third gates having a common junction point and a first capacitor being connected to the common junction point of the second and third gates, the fourth and fifth gates having a common junction point and a second capacitor connected to the common junction point of the fourth and fifth gates.