Power semiconductor device package

Claim 2

A power semiconductor device package comprising: a power semiconductor device die having two major parallel faces, a plurality of aluminum electrodes on one face thereof providing electrical connection to selected regions of the die, a ceramic substrate having two major parallel faces, a plurality of spaced apart contact pads on one face of the substrate, a solderable coating on the opposite face of the substrate, a solderable area on said one substrate face to which the opposite face of the die is soldered whereby said die is in intimate thermal assocation with the substrate for removing head generated in the die, a discrete terminal lead soldered to the contact pads, each of the leads being a tri-layered laminate with a first outer layer of solder on one surface, a second outer layer of aluminum on an opposite surface, and a middle layer of stainless steel, with the solder layer attached to the contact pads on the substrate, a plurality of aluminum filamentary wires electrically connecting said aluminum electrodes and said aluminum outer layer of said terminal leads, a non-rigid material on said one face of said substrate covering said semiconductor device die, said filamentary wires, and an area in close proximity to the filamentary wire interconnections, a generally flat metallic member having a surface, said opposite face of the substrate soldered to the member surface, and an encapsulating rigid plastic covering said non-rigid material, said substrate, and said one surface of said metallic member, but not the opposite surface of said metallic member and outer portions of said terminal leads.

Claim 3

A power integrated circuit package comprising: a power integrated circuit die having two major parallel faces, a plurality of spaced aluminum electrodes on one face thereof providing electrical connection to selected regions of the die, a solderable coating on the opposite face of the die, a ceramic substrate having two parallel major faces, a plurality of spaced apart contact pads located on one face of said substrate, one of said contact pads being larger than the remainder of said contact pads, a solderable coating on the opposite face of said substrate, said opposite face of said die soldered to said larger of said contact pads wherein said die is in thermal association with said substrate for removing heat from said die, a discrete terminal lead soldered to each of the remaining contact pads on said one face of said substrate, each of said leads being a tri-layered laminate with a first outer layer of solder on one surface, a second outer layer of aluminum on an opposite surface, and a middle layer of stainless steel, with the solder layer attached to said contact pads on said substrate, a plurality of aluminum filamentary wires electrically connecting said aluminum electrodes and said aluminum outer layer of said terminal leads which are soldered to said contact pads on the substrate, a non-rigid material on said one face of said substrate covering said integrated circuit die, said filamentary wires, and an area in close proximity to the filamentary wire interconnections, a generally flat metallic member having a surface, said opposite face of said substrate soldered to said member surface, and an encapsulating rigid plastic covering said non-rigid material, said substrate, and said one surface of said metallic member, but not the opposite surface of said metallic member and outer portions of said terminal leads.

Claim 4

A power integrated circuit package comprising: a power integrated circuit die having two major parallel faces, a plurality of spaced aluminum electrodes on one face thereof providing electrical connection to selected regions of the die, a solderable coating on the opposite face of the die, a ceramic substrate having two parallel major faces, a plurality of spaced apart contact pads located on one face of said substrate, one of said contact pads being larger than the remainder of said contact pads, a solderable coating on the opposite face of said substrate, said opposite face of said die soldered to said larger of said contact pads wherein said die is in thermal association with said substrate for removing heat from said die, a discrete terminal lead soldered to each of the remaining contact pads on said one face of said substrate, each of said leads being a tri-layered laminate with a first outer layer of solder on one surface, a second outer layer of aluminum on an opposite surface, and a middle layer of stainless steel, with the solder layer attached to said contact pads on said substrate, a plurality of aluminum filamentary wires electrically connecting said aluminum electrodes and said aluminum outer layer of said terminal leads which are soldered to said contact pads on the substrate, a non-rigid material on said one face of said substrate covering said integrated circuit die, said filamentary wires, and an area in close proximity to the filamentary wire interconnections, a generally flat metallic member having a surface, said opposite face of said substrate soldered to said member surface, and an encapsulating rigid plastic covering said non-rigid material, said substrate, and said one surface of said metallic member, but not the opposite surface of said metallic member and outer portions of said terminal leads.

Claim 5

A power transistor package comprising: a power transistor die having a base region with an aluminum electrode on one face, an emitter region with an aluminum electrode on the same face, and a collector region having a solderable coating on the opposite face, a ceramic substrate having two parallel major faces, three spaced apart contact pads on one face of said subsTrate, one of said contact pads being larger than the other two, a solderable coating on the opposite face of the substrate, said opposite face of said power transistor die soldered to said larger of said contact pads wherein said collector region is electrically connected to said larger contact pad, a discrete terminal lead soldered to each of said contact pads on said one face of said substrate, each of said leads being a tri-layered laminate with a first outer layer of solder on one surface, a second outer layer of aluminum on an opposite surface, and a middle layer of stainless steel, with the solder layer attached to said contact pads on said substrate, an enlarged L-shaped end portion on one of said terminal leads, with said end portion being soldered to said larger contact pad and partially surrounding said power transistor die, an aluminum filamentary wire electrically connecting said base region electrode and said aluminum outer layer of one of the terminal leads soldered to one of the smaller contact pads on said substrate, an aluminum filamentary wire electrically connecting said emitter region electrode and said aluminum outer layer of the terminal lead soldered to the other smaller contact pad on said substrate, a non-rigid material on said one face of said substrate covering said power transistor die, said filamentary wires, and an area on close proximity to the filamentary wire interconnections, a generally flat metallic member having a surface, said opposite face of said substrate soldered to said member surface, and an encapsulating rigid plastic covering said non-rigid material, said substrate and said one surface of said metallic member, but not the opposite surface of said metallic member and outer portions of said terminal leads.

Claim 6

A power transistor package comprising: a power transistor die having a base region with an aluminum electrode on one face, an emitter region with an aluminum electrode on the same face, and a collector region having a solderable coating on the opposite face, a ceramic substrate having two parallel major faces, three spaced apart contact pads on one face of said subsTrate, one of said contact pads being larger than the other two, a solderable coating on the opposite face of the substrate, said opposite face of said power transistor die soldered to said larger of said contact pads wherein said collector region is electrically connected to said larger contact pad, a discrete terminal lead soldered to each of said contact pads on said one face of said substrate, each of said leads being a tri-layered laminate with a first outer layer of solder on one surface, a second outer layer of aluminum on an opposite surface, and a middle layer of stainless steel, with the solder layer attached to said contact pads on said substrate, an enlarged L-shaped end portion on one of said terminal leads, with said end portion being soldered to said larger contact pad and partially surrounding said power transistor die, an aluminum filamentary wire electrically connecting said base region electrode and said aluminum outer layer of one of the terminal leads soldered to one of the smaller contact pads on said substrate, an aluminum filamentary wire electrically connecting said emitter region electrode and said aluminum outer layer of the terminal lead soldered to the other smaller contact pad on said substrate, a non-rigid material on said one face of said substrate covering said power transistor die, said filamentary wires, and an area on close proximity to the filamentary wire interconnections, a generally flat metallic member having a surface, said opposite face of said substrate soldered to said member surface, and an encapsulating rigid plastic covering said non-rigid material, said substrate and said one surface of said metallic member, but not the opposite surface of said metallic member and outer portions of said terminal leads.