Patent US3839104A successfully refreshed from Google Patents.
US3839104A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Fabrication technique for high performance semiconductor devices
Assignee: Texas Instruments Inc
•
Filing: 1972-08-31
•
Granted: 1974-10-01
•
Expires: 1992-08-31
Abstract
Abstract Microwave and pico-second switching transistors are fabricated by a process which includes (1) selective in-diffusion combined with selective out-diffusion to form three resistance levels in the base region; (2) composite diffusion masking for selfalignment of the base contact and emitter locations; and (3) the use of an arsenic-doped oxide diffusion source for the formation of emitter regions prior to doping the base contact locations.
Inventors
- 👤 H Yuan
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 23:06
CPC Classifications
H; H10; H10P; H10P95/00; H10P32/00; H10P32/10; H10P32/14; H10P32/17; H10P32/171; H10W; H10W74/00; H10W74/40; H10W74/43; Y; Y10; Y10S; Y10S438/00; Y10S438/965
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
186 words
A METHOD FOR THE FABRICATION OF A SEMICONDUCTOR DEVICE COMPRISING THE STEPS OF: A. PATTERNING A FIRST DIFFUSION MASK ON A SEMICONDUCTOR SURFACE OF ONE CONDUCTIVITY TYE TO SELECTIVELY EXPOSE AND DEFINE A FIRST SURFACE REGION THEREOF; B. DEPOSITING A SUITABLE CONDUCTIVITY-TYPE-DETERMINING IMPURITY ON SAID FIRST SURFACE REGION FOR SUBSEQUENT REDISTRIBUTION TO FORM A P-N JUNCTION; C. PATTERNING A SECOND DIFFUSION MASK ON SAID FIRST SURFACE REGION TO SELECTIVELY EXPOSE AT LEAST TWO DISCRETE LOCATIONS THEREON; D. REDISTRIBUTING SAID IMPORITY IN THE SEMICONDUCTOR SURFACE WHILE OUT-DIFFUSING A SUBSTANTIAL PORTION OF SAID IMPURITY SELECTIVELY FROM AT LEAST ONE OF SAID DISCRETE LOCATIONS; E. COVERING SAID OUT-DIFFUSED DISCRETE LOCATION WITH AN DHERENT LAYER OF DIELECTRIC MATERIAL CONTAINING AN IMPURITY OF SAID ONE CONDUCTIVITY TYPE; F. INTRODUCING SAID IMPURITY OF SAID ONE TYPE INTO THE SEMICONDUCTOR FROM SAID DOPED DIELECTRIC MATERIAL; G. INTRODUCING AN IMPURITY OF THE OPPOSITE CONDUCTIVITY TYPE INTO THE SEMICONDUCTOR AT ONE OR MORE OF SAID DISCRETE LOCATIONS NOT COVERED BY SAID DOPED DIELECTRIC MATERIAL H. REMOVING SAID DOPED DIELECTRIC FROM SAID DISCRETE LOCATION; AND I. FORMING OHMIC CONTACTS TO THE SEMICONDUCTOR AT SIAD DISCRETE LOCATIONS.
Claim 2
Independent Claim
186 words
A METHOD FOR THE FABRICATION OF A SEMICONDUCTOR DEVICE COMPRISING THE STEPS OF: A. PATTERNING A FIRST DIFFUSION MASK ON A SEMICONDUCTOR SURFACE OF ONE CONDUCTIVITY TYE TO SELECTIVELY EXPOSE AND DEFINE A FIRST SURFACE REGION THEREOF; B. DEPOSITING A SUITABLE CONDUCTIVITY-TYPE-DETERMINING IMPURITY ON SAID FIRST SURFACE REGION FOR SUBSEQUENT REDISTRIBUTION TO FORM A P-N JUNCTION; C. PATTERNING A SECOND DIFFUSION MASK ON SAID FIRST SURFACE REGION TO SELECTIVELY EXPOSE AT LEAST TWO DISCRETE LOCATIONS THEREON; D. REDISTRIBUTING SAID IMPORITY IN THE SEMICONDUCTOR SURFACE WHILE OUT-DIFFUSING A SUBSTANTIAL PORTION OF SAID IMPURITY SELECTIVELY FROM AT LEAST ONE OF SAID DISCRETE LOCATIONS; E. COVERING SAID OUT-DIFFUSED DISCRETE LOCATION WITH AN DHERENT LAYER OF DIELECTRIC MATERIAL CONTAINING AN IMPURITY OF SAID ONE CONDUCTIVITY TYPE; F. INTRODUCING SAID IMPURITY OF SAID ONE TYPE INTO THE SEMICONDUCTOR FROM SAID DOPED DIELECTRIC MATERIAL; G. INTRODUCING AN IMPURITY OF THE OPPOSITE CONDUCTIVITY TYPE INTO THE SEMICONDUCTOR AT ONE OR MORE OF SAID DISCRETE LOCATIONS NOT COVERED BY SAID DOPED DIELECTRIC MATERIAL H. REMOVING SAID DOPED DIELECTRIC FROM SAID DISCRETE LOCATION; AND I. FORMING OHMIC CONTACTS TO THE SEMICONDUCTOR AT SIAD DISCRETE LOCATIONS.
Claim 3
Dependent Claim
28 words
A method as in claim 1 wherein said semiconductor is silicon, said first diffusion mask is silicon oxide, and said second diffusion mask comprises silicon oxide and nitride.
Claim 4
Dependent Claim
23 words
A method as in claim 2 wherein said second diffusion mask comprises a layer of silicon oxide and a layer of silicon nitride.
Claim 5
Dependent Claim
30 words
A method as in claim 1 wherein said semiconductor is silicon, and wherein said adherent layer of dielectric material containing impurities of said one conductivity type comprises arsenic-doped silicon oxide.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-09-30 | 1978-04-01 | 1978-10-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-09-30 | 1982-04-01 | 1982-10-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-09-30 | 1986-04-01 | 1986-10-01 | $7700.00 | Window Closed / Lapsed |