Patent US3838262A successfully refreshed from Google Patents.
US3838262A
Expired / Lapsed
US
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Four-quadrant multiplier circuit
Assignee: US Philips Corp
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Filing: 1973-07-25
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Granted: 1974-09-24
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Expires: 1993-07-25
Abstract
Abstract A four-quadrant multiplier circuit, constituted in a known manner by three differential stages, one stage of which receives the x-signal and supplies the current for the two other stages, which receive the y-signal in parallel. From the output currents of these two last-mentioned differential stages such sum currents are formed with the aid of multiple current mirrors that these currents are suitable to be applied to the two inputs of the circuit as negative-feedback currents. By also applying the input signals as currents an effective negative feedback system is obtained.
Inventors
- 👤 De Plassche R Van
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 06:05
CPC Classifications
G; G06; G06G; G06G7/00; G06G7/12; G06G7/16
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
341 words
A four-quadrant multiplier circuit for multiplying a first and a second input signal, comprising a first differential stage with a first and a second transistor, to whose control electrodes the first input signal is applied as a differential signal and whose common-electrode circuit includes a current source, a second differential stage with a third and a fourth transistor, whose common-electrode circuit includes the main current path of the first transistor and to whose control electrodes the second input signal is applied as a differential signal, and a third differential stage with a fifth and a sixth transistor, whose common-electrode circuit includes the main current path of the second transistor, the control electrode of the fifth transistor being coupled to the control electrode of the fourth transistor and the control electrode of the sixth transistor to the control electrode of the third transistor, and means for obtaining the desired output signal proportional to the product of the two input signals, including means for combining the output currents of the transistors of the second and the third differential stage, characterized in that the circuit comprises a first multiple current mirror, which supplies a first and a second output current, which are in a fixed relationship with the output current of the fourth transistor which is applied the input of this first current mirror, first adding means by means of which a first sum current is formed from the output current of the third transistor and the first output current of the first current mirror, second adding means by means of which A second sum current is formed from the output current of the fifth transistor and the second output current of the first current mirror, first negative-feedback means via which the first sum current is fed back degeneratively to the input of the first differential stage and second negative-feedback means via which the second sum current is fed back degeneratively to the input of the second differential stage, the two input signals being applied to said inputs of the multiplier circuit as currents.
Claim 2
Dependent Claim
341 words
A four-quadrant multiplier circuit for multiplying a first and a second input signal, comprising a first differential stage with a first and a second transistor, to whose control electrodes the first input signal is applied as a differential signal and whose common-electrode circuit includes a current source, a second differential stage with a third and a fourth transistor, whose common-electrode circuit includes the main current path of the first transistor and to whose control electrodes the second input signal is applied as a differential signal, and a third differential stage with a fifth and a sixth transistor, whose common-electrode circuit includes the main current path of the second transistor, the control electrode of the fifth transistor being coupled to the control electrode of the fourth transistor and the control electrode of the sixth transistor to the control electrode of the third transistor, and means for obtaining the desired output signal proportional to the product of the two input signals, including means for combining the output currents of the transistors of the second and the third differential stage, characterized in that the circuit comprises a first multiple current mirror, which supplies a first and a second output current, which are in a fixed relationship with the output current of the fourth transistor which is applied the input of this first current mirror, first adding means by means of which a first sum current is formed from the output current of the third transistor and the first output current of the first current mirror, second adding means by means of which A second sum current is formed from the output current of the fifth transistor and the second output current of the first current mirror, first negative-feedback means via which the first sum current is fed back degeneratively to the input of the first differential stage and second negative-feedback means via which the second sum current is fed back degeneratively to the input of the second differential stage, the two input signals being applied to said inputs of the multiplier circuit as currents.
Claim 3
Dependent Claim
96 words
A four-quadrant multiplier circuit as claimed in claim 1, characterized in that the first adding means includes a second current mirror to whose input the output current of the third transistor is applied and whose output current together with the first output current of the first current mirror constitutes the first sum current and that the second adding means includes a third current mirror, to whose input the output current of the fifth transistor is applied, and whose output current together with the second output current of the first current mirror constitutes the second sum current.
Claim 4
Dependent Claim
99 words
A four-quadrant multiplier circuit as claimed in claim 2, characterized in that the second current mirror is of a multiple type and supplies a first and a second output current, its first output current being used for the formation of the first sum current, and that third adding means are provided by means of which a third sum current is formed from the output current of the sixth transistor and the second output current of the second current mirror, said third sum current being fed back degeneratively via third negative-feedback means to the input of the second differential stage.
Claim 5
Dependent Claim
99 words
A four-quadrant multiplier circuit as claimed in claim 2, characterized in that the third current mirror is of a multiple type and supplies a first and a second output current, its first output current being used for the formation of the second sum current, and that third adding means are provided by means of which a fourth sum current is formed from the output current of the sixth transistor and the second output current of the third current mirror, said fourth sum current being fed back degeneratively via fourth negative-feedback means to the input of the first differential stage.
Claim 6
Dependent Claim
51 words
A four-quadrant multiplier circuit as claimed in claim 3, characterized in that the third adding means includes a fourth current mirror, to whose input the output current of the sixth transistor is applied and whose output current is used for the formation of the sum current supplied by said adding means.
Claim 7
Dependent Claim
155 words
A four-quadrant multiplier circuit as claimed in claim 3, characterized in that the third current mirror is of a multiple type and supplies a first and a second output current, its first output current being used for the formation of the second sum current, and that third adding means are provided by means of which a fourth sum current is formed from the output current of the sixth transistor and the second output current of the third current mirror, said fourth sum current being fed back degeneratively via fourth negative-feedback means to the input of the first differential stage, the third adding means includes a multiple current mirror, to whose input the output current of the sixth transistor is applied and which supplies a first and a second output current, said first current being used for the formation of the third sum current and said second current for the formation of the fourth sum current.
Claim 8
Dependent Claim
76 words
A four-quadrant multiplier circuit as claimed in claim 3, characterized in that the second and the third negative-feedback means are connected to the control electrode of one and the same transistor of the second differential stage, one of said negative-feedback means establishing a direct connection between the relevant adding means and said control electrode, and the other negative-feedback means including a current mirror by means of which an inversion of the relevant sum current is obtained.
Claim 9
Dependent Claim
77 words
A four-quadrant multiplier circuit as claimed in claim 4, characterized in that the first and the fourth negative-feedback means are connected to the control electrode of one and the same transistor of the first differential stage, one of the said negative-feedback means establishing a direct connection between the relevant adding means and said control electrode, and the other negative-feedback means including a current mirror by means of which an inversion of the relevant sum current is obtained.
Claim 10
Dependent Claim
50 words
A four-quadrant multiplier circuit as claimed in claim 6, characterized in that the two input signals are applied to the first and the second differential stage in a balanced manner and the negative-feedback currents destined for a certain input are also applied to the relevant input in a balanced manner.
Claim 11
Dependent Claim
49 words
A four-quadrant multiplier circuit as claimed in claim 4 wherein the third adding means includes a fourth current mirror, to whose input the output current of the sixth transistor is applied and whose output current is used for the formation of the sum current supplied by said adding means.
Claim 12
Dependent Claim
76 words
A four-quadrant multiplier circuit as claimed in claim 5 characterized in that the second and the third negative-feedback means are connected to the control electrode of one and the same transistor of the second differential stage, one of said negative-feedback means establishing a direct connection between the relevant adding means and said control electrode, and the other negative-feedback means including a current mirror by means of which an inversion of the relevant sum current is obtained.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-09-23 | 1978-03-25 | 1978-09-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-09-23 | 1982-03-25 | 1982-09-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-09-23 | 1986-03-25 | 1986-09-24 | $7700.00 | Window Closed / Lapsed |