Four quadrant multiplier using bi-polar digital analog converter

Claim 1

A four quadrant multiplier circuit for obtaining the bi-polar product of a pair of signed signal voltages, the first of which is a signed analog voltage and the second of which is a signed voltage in the form of a digital word, comprising, a pair of reference conductors, means for applying said signed analog voltage to the first of said reference conductors, means for producing the inverse of said signed analog voltage and applying same to the second of said reference conductors, a resistor matrix network having a current summing node therein, a plurality of bi-polar switch means equal in number to the number of binary bits in said digital word, each bi-polar switch means being connected between said pair of reference conductors and selectively operated in response to a voltage, each constituting a binary bit, each said voltage constituting said binary bits being greater in magnitude than the maximum magnitude of the voltages on said reference conductors, respectively, to connect one of said reference conductors to said resistor matrix and cause a current to flow therein to said summing node according to the binary significance thereof, respectively, and an operational amplifier having one input thereof connected to said current summing node and the other input thereof connected to ground.

Claim 7

A method of obtaining the bi-polar product of two, signed signal voltages one of said signed signal voltages being an analog voltage and the other being a binary code permutation of the binary word, equivalent of the other of said signed signal voltages, comprising, generating the inverse of said signed analog signal voltage and connecting said signed signal voltage and the inverse of said signed signal voltage to a series connected resistor matrix at a plurality of points therein in accordance with the binary code permutation of the binary word equivalent of the other of said signed signal voltages to cause a current to flow in said series resistor matrix to a summing node, said current being the sum of the binary weighted currents and having a magnitude and sign dependent on the said binary word equivalent and the magnitude and sign of said analog voltage.

Claim 8

A method of obtaining the bi-polar product of two, signed signal voltages one of said signed signal voltages being an analog voltage and the other being a binary code permutation of the binary word, equivalent of the other of said signed signal voltages, comprising, generating the inverse of said signed analog signal voltage and connecting said signed signal voltage and the inverse of said signed signal voltage to a series connected resistor matrix at a plurality of points therein in accordance with the binary code permutation of the binary word equivalent of the other of said signed signal voltages to cause a current to flow in said series resistor matrix to a summing node, said current being the sum of the binary weighted currents and having a magnitude and sign dependent on the said binary word equivalent and the magnitude and sign of said analog voltage.