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US3836409A Expired / Lapsed US ⏱️ 0.0 years remaining

Uniplanar ccd structure and method

Assignee: Fairchild Semiconductor Corp
•
Filing: 1972-12-07
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Granted: 1974-09-17
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Expires: 1992-12-07
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Abstract

Abstract A CCD structure is made by forming an insulating layer over semiconductor material, forming a substantially uniform layer of polycrystalline semiconductor material over the insulating layer, and then using the polycrystalline semiconductor material during the formation of gate electrodes associated with the CCD structure and associated MOS readout circuitry to prevent the diffusion of impurities into the underlying semiconductor material.

Inventors

  • 👤 G Amelio
  • 👤 P Salsbury

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-23 18:23
CPC Classifications
H; H10; H10D; H10D44/00; H10D44/40; H10D44/45; H10D44/472; H10D62/00; H10D62/10; H10D62/17; H10D62/213; H10D62/335; H10D99/00; H10P; H10P95/00

Claims Analysis

Total Claims: 12
Claim 1
Independent Claim 186 words
The method of claim 1 wherein the steps of forming an opening through each of said at least two regions of said first layer of insulation and of forming a plurality of openings in said second layer of insulation to expose the top surfaces of a plurality of regions of polycrystalline silicon comprises: forming a third layer of insulation over the top surface of the second layer of insulation and the exposed surface of the first layer of insulation, said third layer and said first layer together being capable of masking impurities to be diffused into said semiconductor material; removing portions of said third layer of insulation and said second layer of insulation to expose surfaces of said plurality of regions of said polycrystalline silicon and removing portions of said third layer of insulation and said first layer of insulation to expose the surfaces of at least two selected regions of said semiconductor material, the exposed surfaces of said at least two seleCted regions occupying a smaller surface area than said at least two openings in said second layer of insulation and in said polycrystalline silicon.
Claim 2
Dependent Claim 27 words
The method of claim 1 including the additional step of removing said polycrystalline silicon overlying the field of said combined charge coupled device and said MOS transistor.
Claim 3
Dependent Claim 149 words
The method of claim 3 wherein said step of removing the polycrystalline silicon overlying the field comprises the steps of: forming a fourth layer of insulation over at least the surfaces of said at least two selected regions of said semiconductor material, said plurality of openings in said second layer of insulation, and the portions of said second layer of insulation located between said plurality of openings and removing the portions of said first, second, third and fourth layers of insulation not overlying or underlying the surfaces of said at least two selected regions of said semiconductor material, said plurality of openings in said second layer of insulation, and the portions of said second layer of insulation located between said plurality of openings until polycrystalline silicon or underlying semiconductor material is exposed; and removing the exposed polycrystalline silicon material to expose portions of the underlying first layer of insulation.
Claim 4
Dependent Claim 47 words
The method of claim 4 including the step of: forming a fifth layer of insulation over the top surface of the structure; and forming openings in said fifth layer of insulation to expose the top surface of said at least two selected regions of said semiconductor material.
Claim 5
Dependent Claim 28 words
The method of claim 5 including the additional step of forming contacts to said at least two selected regions through said openings in said fifth layer of insulation.
Claim 6
Dependent Claim 37 words
The method of claim 1 wherein one of said plurality of regions of said polycrystalline silicon is located over said first layer of insulation between two of said at least two selected regions of said semiconductor material.
Claim 7
Dependent Claim 18 words
The method of claim 1 wherein said first layer of insulation comprises an insulating layer of uniform thickness.
Claim 8
Dependent Claim 14 words
The method of claim 1 wherein said first layer of insulation comprises silicon oxide.
Claim 9
Dependent Claim 67 words
The method of claim 1 including the additional step of forming a multiplicity of barrier regions in said semiconductor material adjacent the interface between said semiconductor material and said first layer of insulation, said multiplicity of barrier regions being formed to appropriately control the electrical potential distribution in the underlying semiconductor material as required for the operation of a two-phase charge coupled device in said semiconductor material.
Claim 10
Dependent Claim 62 words
The method of claim 10 wherein the step of forming said multiplicity of barrier regions comprises the step of forming a multiplicity of ion-implanted regions of about 2000 angstroms thickness adjacent the interface between said semiconductor material and said first layer of insulation, said barrier regions being formed with a surface charge density of about 8 X 1011 ions per square centimeter.
Claim 11
Independent Claim 276 words
A method for making a charge coupled device structure and an MOS transistor in a single piece of semiconductor material which comprises the following steps: forming a channel stop region adjacent one surface of semiconductor material, said channel stop region forming a closed path around the surface of a portion of said semiconductor material in which is to be formed a charge coupled device and an MOS transistor, at least part of the semiconductor material outside of said portion comprising the field of said structure; forming an insulating layer over said one surface of said semiconductor material; forming a uniform layer of polycrystalline semiconductor material over said insulating layer; removing the polycrystalline semiconductor material formed over the field of said structure and over selected regions of said insulating layer to leave on said insulating layer selected shapeS of polycrystalline semiconductor material; forming openings through said selected regions of said insulating layer to expose the surfaces of selected regions of said semiconductor material, said openings being formed adjacent selected portions of said polycrystalline semiconductor material left on said insulating layer and each opening through said insulating layer being smaller in area than the corresponding opening through said polycrystalline semiconductor material; forming a second insulating layer over said polycrystalline semiconductor material leaving exposed the surfaces of a plurality of regions of said polycrystalline semiconductor material; and forming in said regions of semiconductor material the surfaces of which are exposed by said openings, regions of a conductivity type opposite to the conductivity type of said semiconductor material and simultaneously forming in said plurality of regions of polycrystalline semiconductor material a plurality of conductive regions of said opposite conductivity type.
Claim 12
Dependent Claim 11 words
The method of claim 1 wherein said semiconductor material is silicon.

References Cited (Backward Citations)

US3475234A Cited
US3699646A Cited
US3711753A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1977-09-16 1978-03-18 1978-09-17 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1981-09-16 1982-03-18 1982-09-17 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1985-09-16 1986-03-18 1986-09-17 $7700.00 Window Closed / Lapsed

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