Patent US3828320A successfully refreshed from Google Patents.
US3828320A
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Shared memory addressor
Assignee: Unisys Corp
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Filing: 1972-12-29
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Granted: 1974-08-06
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Expires: 1992-12-29
Abstract
Abstract An access unit for a shared memory for use in a microprogrammable processor is provided utilizing a multiplexing scheme. Two functionally different inputs, one for data, the other for microinstructions are exclusively gated to memory in synchronization with microprogram control timing cycles to permit accessing the memory at separate times via a single channel.
Inventors
- 👤 B Dinerman
- 👤 F Schroeder
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 20:32
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/22; G06F9/24; G06F12/00; G06F12/02; G06F12/0223; G06F13/00; G06F13/14; G06F13/16; G06F13/18; G06F9/26
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
243 words
In a microprogrammable parallel bit digital computer; having a shared memory for storing information which includes both microinstructions and data-words in separable portions therein and having a central processor associated with said memory, said processor including a memory control wherein said memory control has a memory input register for feeding said shared memory, said processor also including a microprogram control for storing both microinstructions and data-words in separable portions therein which includes a microprogram address register and a memory address register each of which addresses microinstruction locations and data locations of said memory respectively, said processor also including timing circuitry for generating a ''''data-cycle'''' signal and a data cycle signal and an ''''externalload'''' signal and a external load signal; and peripheral devices; an improved memory addressing unit comprising: first multiplexing means coupled to said microprogram address register, said memory address register and said shared memory for feeding microinstruction addresses from said microprogram address register and data addresses from said memory address register to said shared memory via common memory address lines; second multiplexing means connected to said processor including said memory input register and said timing circuitry for feeding information from said peripheral devices or said central processor to said memory via common memory input lines; and demultiplexing means associated with said memory control, said microprogram control, said memory and said timing circuitry for separating information from said memory into data words for said memory control and microinstruction words for said microprogram control.
Claim 2
Dependent Claim
243 words
In a microprogrammable parallel bit digital computer; having a shared memory for storing information which includes both microinstructions and data-words in separable portions therein and having a central processor associated with said memory, said processor including a memory control wherein said memory control has a memory input register for feeding said shared memory, said processor also including a microprogram control for storing both microinstructions and data-words in separable portions therein which includes a microprogram address register and a memory address register each of which addresses microinstruction locations and data locations of said memory respectively, said processor also including timing circuitry for generating a ''''data-cycle'''' signal and a data cycle signal and an ''''externalload'''' signal and a external load signal; and peripheral devices; an improved memory addressing unit comprising: first multiplexing means coupled to said microprogram address register, said memory address register and said shared memory for feeding microinstruction addresses from said microprogram address register and data addresses from said memory address register to said shared memory via common memory address lines; second multiplexing means connected to said processor including said memory input register and said timing circuitry for feeding information from said peripheral devices or said central processor to said memory via common memory input lines; and demultiplexing means associated with said memory control, said microprogram control, said memory and said timing circuitry for separating information from said memory into data words for said memory control and microinstruction words for said microprogram control.
Claim 3
Dependent Claim
145 words
The apparatus of claim 1 wherein said first multiplexing means comprises: a first plurality of ''''and'''' gates, each having an input connected to respective bit portions of said memory control and each being enabled on another input by said ''''data-cycle'''' signal from said timing circuitry to pass a data word address bit; a second plurality of ''''and'''' gates each having an input connected to respective bit positions of said microprogram control and each being enabled on another input by said ''''data-cycle'''' signal to pass a microinstruction address bit; and a first plurality of ''''or'''' gates each being connected to a respective address bit position of said first plurality of ''''and'''' gate and also to a corresponding address bit position one of said second plurality of ''''and'''' gate, the output of each of said ''''or'''' gates being connected to respective memory address lines of said memory.
Claim 4
Dependent Claim
134 words
The apparatus of claim 2 wherein said demultiplexing means comprises: a plurality of parallel shift registers, an input of each of said shift registers being connected to a respective output word bit position of said shared memory, said registers being clocked to pass said information by the presence of said ''''data-cycle'''' signal from said timing circuitry; a plurality of groups of interfacing gates, each of said gates within a group being fed by a respective output bit position of a said shift register connected to said group; a data bus connected to each of said outputs of said plurality of interfacing gates and said memory control; a plurality of word information lines, each line being individually connected between a respective word bit position input of said plurality of shift registers and said microprogram control.
Claim 5
Dependent Claim
145 words
The apparatus of claim 3 wherein said second multiplexing means comprises: a third plurality of ''''and'''' gates each having a respective input connected to said central processor and being enabled to pass a word from said central processor by the presence of said ''''external-load'''' signal on the another input; a fourth plurality of ''''and'''' gates each having a respective input connected to a bit position of said memory input register and being enabled to pass a word from said peripheral devices by said external load signal said timing circuitry on another input; and a second plurality of ''''or'''' gates each being connected to a respective one of said third plurality of ''''and'''' gates and to respective one of said fourth plurality of ''''and'''' gates, the output of a respective one of said ''''or'''' gates being connected to a respective one of said shared memory inputs.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-08-05 | 1978-02-04 | 1978-08-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-08-05 | 1982-02-04 | 1982-08-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-08-05 | 1986-02-04 | 1986-08-06 | $7700.00 | Window Closed / Lapsed |