Signal duration sensing circuit

Claim 2

The combinatioN comprising: input means adapted to receive an input signal to be sampled; first and second signal storing means; first means coupled to said input means and responsive to said input signal for setting said first storing means to a condition indicative of the value of said input signal during a sampling interval; second means responsive to the signal stored in said first storing means for shifting the signal stored in said first storing means to said second storing means during a shifting interval succeeding said sampling interval and for then storing said signal in said second storing means; and means for coupling to said first means the signal stored in said second storing means for preventing an input signal having a duration shorter than the interval between said sampling and shifting intervals from altering the condition of said first storing means.

Claim 3

The combination as claimed in claim 1 further including feed through means coupled to said first and second means for concurrently enabling said first and second means for passing, without delay, said input signal through said first means and through said second means.

Claim 4

The combination as claimed in claim 1 wherein said first and second storing means are two state storage means, each having set and reset inputs and two outputs, one output being the complement of the other.

Claim 5

The combination as claimed in claim 3 wherein said first means includes means for receiving a sampling pulse during said sampling interval; and wherein said second means includes means for receiving a shift pulse during said shifting interval.

Claim 6

The combination as claimed in claim 3, wherein said first gating means includes an inverter for inverting said input signal, and wherein said first means includes one path coupled to said first storing means controlled by said input signal and a second path coupled to said first storing means controlled by the complement of the input signal.

Claim 7

The combination comprising: an input point for the application thereto of input signals; first and second two state storage means each having a set input, a reset input, an output and a complementary output; first gating means coupled between said input point and the inputs of said first storage means; means for applying sampling pulses to set first gating means for sampling said input signals and setting said first storage means to a binary condition indicative of the binary condition of the input signal; second gating means coupled between the outputs of said first storage means and the inputs of said second storage means; means for applying shift pulses to said second gating means for setting said second storage means to the same binary conditions as said first storage means where each shift pulse occurs a time T after the occurrence of a sampling pulse; and means coupling the outputs of said second storage means to said first gating means for controlling the transfer of said input signals to said first storage means and determining the state of said first storage means in the absence of sampling pulses.

Claim 8

The combination comprising: an input point for the application thereto of input signals; first and second two state storage means each having a set input, a reset input, an output and a complementary output; first gating means coupled between said input point and the inputs of said first storage means; means for applying sampling pulses to set first gating means for sampling said input signals and setting said first storage means to a binary condition indicative of the binary condition of the input signal; second gating means coupled between the outputs of said first storage means and the inputs of said second storage means; means for applying shift pulses to said second gating means for setting said second storage means to the same binary conditions as said first storage means where each shift pulse occurs a time T after the occurrence of a sampling pulse; and means coupling the outputs of said second storage means to said first gating means for controlling the transfer of said input signals to said first storage means and determining the state of said first storage means in the absence of sampling pulses.

Claim 9

The combination as claimed in claim 6 wherein said first gating means includes means which in response to an input signal of same binary significance as that present at the outputs of said second storage means apply to the inputs of said first storage means signals of a value to maintain or restore its output to the same binary condition as the output and which in response to an input signal of other binary significance than that present at the outputs of the second storage means maintains the output of said first sorage means in the condition to which it was set when the sampling pulse was present.

Claim 10

The combination as claimed in claim 5, further including direct feed through means coupled to said first and second gating means for concurrently enabling both of said gating means for passing, without delay, said input signals through said gating means.

Claim 11

The cOmbination as claimed in claim 6 wherein said first gating means includes an inverter for inverting said input signals and wherein said gating means includes one path coupled to one input of said first storage means controlled by the input signal and a second path coupled to the other input of said first storage means controlled by the inverse of said input signal.

Claim 12

A circuit for producing output signals of first significance in response to input signals having a first value for a period greater than T and for producing output signals of second significance in response to input signals having a second value for a period greater than T, where said period includes a sampling pulse followed by a shift pulse, comprising: first and second flip-flops, each flip-flop having a set input and a reset input, an output terminal and a complementary output terminal; first gating means for periodically sampling said input signals and producing signals in response thereto which are applied to the inputs of said first flip-flop; second gating means for periodically shifting the signals produced at the outputs of said first flip-flop to the inputs of said second flip-flop, where each shift operation occurs a time T after a sampling operation; and means for comparing the input signal with the output of the second flip-flop for controlling the setting of the first flip-flop; said first flip-flop being reset to its preceeding condition for all input signals whose duration is less than T.

Claim 13

A circuit for producing output signals of first significance in response to input signals having a first value for a period greater than T and for producing output signals of second significance in response to input signals having a second value for a period greater than T, where said period includes a sampling pulse followed by a shift pulse, comprising: first and second flip-flops, each flip-flop having a set input and a reset input, an output terminal and a complementary output terminal; first gating means for periodically sampling said input signals and producing signals in response thereto which are applied to the inputs of said first flip-flop; second gating means for periodically shifting the signals produced at the outputs of said first flip-flop to the inputs of said second flip-flop, where each shift operation occurs a time T after a sampling operation; and means for comparing the input signal with the output of the second flip-flop for controlling the setting of the first flip-flop; said first flip-flop being reset to its preceeding condition for all input signals whose duration is less than T.