Semi-conductor memory device arrangements

Claim 2

A memory device array comprising two sets of conductors, a plurality of semi-conductor memory devices each associated with an individual pair of conductors chosen one from each set and having a first and a second electrode, a plurality of pairs of resistors each associated with a respective memory device, each resistor in the pair connecting the said first electrode of the memory device to a respective one of the associated pair of conductors, each memory device being switchable from a first state to a second state in response to a bias waveform of predetermined and essentially uninterrupted time duration and having first and second components, said first component being of short duration relative to said predetermined time duration and of amplitude exceeding a predetermined value and said second component being of large duration relative to first component and of amplitude less than said predetermined value, and means for enabling connection of said second electrodes of the memory device to a source of potential providing separate portions of said bias waveforms.

Claim 3

A memory device array as claimed in claim 1, in which the array is formed on a substrate.

Claim 4

A memory device array as claimed in claim 2, in which the substrate carries a plurality of parallel conductors, alternate ones of which constitute one of said sets of conductors and the remaining alternate ones of which constitute means for enabling connection of the second electrodes to a source of potential; a layer of insulating material, covering the substrate and the conductor and having means defining apertures therein where said layer is covering pre-determined ones of the conductors; a plurality of amorphous semi-conductor memory device elements formed one in each of the apertures in said insulating layer where said layer is covering conductors which constitute said connecting means; metal electrodes formed on top of the memory device elements; a second plurality of parallel conductors which constitutes the other of said sets of conductors formed on the surface of said insulating layer; a first plurality of resiStive elements each positioned to connect said metal electrodes of an individual device to an individual pre-determined area of one of said first set of conductors through an aperture in said layer of insulating material and a second plurality of resistive elements each positioned to connect said metal electrode of an individual device to one of the conductors of said second plurality of conductors.

Claim 5

A memory device array as claimed in claim 3 in which the conductors are of gold.

Claim 6

A memory device as claimed in claim 3 in which the conductors are formed by a layer of gold deposited on chromium or molybdenum.

Claim 7

A memory device array as claimed in claim 3 in which the said insulating material is silicon chromide.

Claim 8

A memory device array as claimed in claim 3 in which the amorphous semi-conductor material is chalcogenide glass.

Claim 9

In combination a memory device array comprising two sets of conductors, a plurality of semi-conductor memory devices each associated with an individual pair of conductors chosen one from each set and having a first and a second electrode, a plurality of pairs of resistors each associated with a respective memory device, each resistor in the pair connecting the said first electrode of the memory device to a respective one of the associated pair of conductors, and means for enabling connection of said second electrodes of the memory device to a source of potential, and a control voltage source for controlling the devices of the memory array into the conductive state, the said source being adapted first to apply across any device to be rendered stably conductive a first voltage pulse having a pre-determined duration at least sufficient to drive the device into a conductive state and subsequently to apply a lower voltage to maintain a flow of current through the device of such a level and for such a time as to render the conductive state permanent.

Claim 10

In combination a memory device array comprising two sets of conductors, a plurality of semi-conductor memory devices each associated with an individual pair of conductors chosen one from each set and having a first and a second electrode, a plurality of pairs of resistors each associated with a respective memory device, each resistor in the pair connecting the said first electrode of the memory device to a respective one of the associated pair of conductors, and means for enabling connection of said second electrodes of the memory device to a source of potential, and a control voltage source for controlling the devices of the memory array into the conductive state, the said source being adapted first to apply across any device to be rendered stably conductive a first voltage pulse having a pre-determined duration at least sufficient to drive the device into a conductive state and subsequently to apply a lower voltage to maintain a flow of current through the device of such a level and for such a time as to render the conductive state permanent.

Claim 11

A combination as claimed in claim 8, in which, to render the device conductive during operation, the first voltage pulse is applied between the second electrode of the device to be set and one of the pair of conductors connected to the first electrode of that device and the lower magnitude voltage is subsequently applied over at least part of its duration across the second electrode of the device and the other one of the pair of conductors.

Claim 12

A combination as claimed in claim 9 in which the lower magnitude voltage is applied during the first part of its duration via said other of the pair of conductors and for the remainder of its duration via said one of the pair of conductors.

Claim 13

A memory device array comprising, in combination: two sets of conductors arranged as M number of x lines and N number of y lines each x including N resistors and each y line including M resistors, the resistors of the x lines being connected to the resistors of the y lines to define MN cross points; a plurality of MN of semi-conductor memory devices each having first and second electrodes and the first electrodes of said memory device being connected individually to said cross points, each memory device being switchable from a first state to a second state in response to a bias waveform of selected and essentially uninterrupted time duration having successive first and second components, said first component being of small duration relative to said selected time duration and of amplitude exceeding a predetermined value and said second component being of large duration relative to said first component and of amplitude less than said predetermined value; and potential source means connected to said x and y lines and to said second electrodes of the memory devices for selectively applying bias waveforms to said memory devices, at least said first components of the selectively applied bias waveforms being applied to said x lines and at least a portion of said second components of the selectively applied waveforms beiNg applied to said y lines whereby to write in information corresponding to the selectively applied waveforms.

Claim 14

A memory device array comprising, in combination: two sets of conductors arranged as M number of x lines and N number of y lines each x including N resistors and each y line including M resistors, the resistors of the x lines being connected to the resistors of the y lines to define MN cross points; a plurality of MN of semi-conductor memory devices each having first and second electrodes and the first electrodes of said memory device being connected individually to said cross points, each memory device being switchable from a first state to a second state in response to a bias waveform of selected and essentially uninterrupted time duration having successive first and second components, said first component being of small duration relative to said selected time duration and of amplitude exceeding a predetermined value and said second component being of large duration relative to said first component and of amplitude less than said predetermined value; and potential source means connected to said x and y lines and to said second electrodes of the memory devices for selectively applying bias waveforms to said memory devices, at least said first components of the selectively applied bias waveforms being applied to said x lines and at least a portion of said second components of the selectively applied waveforms beiNg applied to said y lines whereby to write in information corresponding to the selectively applied waveforms.

Claim 15

A memory device array according to claim 11 wherein said potential source means applies said first components and a terminal portion of said second components to said x lines and bridging portions of said second components to said y lines.

Claim 16

A memory device array according to claim 12 wherein said potential source means includes means for sequentially applying a voltage less than said predetermined value to said x lines while maintaining the remaining x lines at reference potential and means for sequentially reading the potential appearing at said y lines whereby individually to read the states of said memory devices.

Claim 17

A memory device array according to claim 11 wherein said potential source means includes means for sequentially applying a voltage less than said predetermined value to said x lines while maintaining the remaining x lines at reference potential and means for sequentially reading the potentials appearing at said y lines whereby individually to read the states of said memory devices.

Claim 18

A memory device array as defined in claim 11 wherein said potential source means writes in information line-by-line.

Claim 19

A memory device array as defined in claim 12 wherein said potential source means writes in information line-by-line.

Claim 20

A memory device array as defined in claim 13 wherein said potential source means writes in information line-by-line.

Claim 21

A memory device array as defined in claim 14 wherein said potential source means writes in information line-by-line.