Digital ssb transmitter

Claim 1

A single sideband transmitter for a data communication system, comprising encoder means for receiving a data input, a clock generator, a digital shaping filter, means for connecting the output of said encoder means to said digital shaping filter, a sine-cosine generator, first frequency divider means connected to the output of said clock generator for producing a first, data clock signal for controlling the data output rate of said encoder and a second, digital filter clock signal for controlling said digital filter, second frequency divider means connected to the output of said clock generator means for producing a square wave input to said sine-cosine generator having a frequency which is sub-multiple of the clock generator frequency and for producing a carrier clock signal for controlling said sine-cosine generator, said digital shaping filter including means for converting the data input thereto from said encoder means into a first and second equally delayed outputs, said first output comprising the Inverse Fourier transform of the response of a substantially ideal lowpass filter to said input from said encoder means and said second output comprising the Inverse Hilbert transform of the response of a substantially ideal lowpass filter to said input from said encoder means, and said sine-cosine generator comprising means for converting the input thereto into a first inphase carrier component comprising a cosine wave signal and a second, quadrature carrier component comprising a sine wave signal, first multiplying means for multiplying said cosine wave signal by the Fourier output of said digital shaping filter to produce a first output and second multiplying means for multiplying signal sine wave by the Hilbert output of said digital shaping filter to produce a second output, and summing means for summing said first and second outputs to produce a single sideband, suppressed carrier modulated signal, said first frequency dividing means comprising a first frequency divider for dividing the clock generator frequency by a first predetermined factor, N, to produce said digital filter clock signal and a second frequency divider for dividing the output of said first frequency divider by a second predetermined factor, N1, so as to produce said data clock signal and said second frequency divider means comprising a third frequency divider for dividing the clock generator frequency by a third predetermined factor, M, to produce said carrier clock signal and a fourth frequency divider for dividing the output of said third frequency divider by a fourth predetermined factor, M1, to produce said input to said sine-cosine generator, said factors being related by the formula fcMM1 fdNN1 wherein fc is the carrier frequency and fd is the data rate, said digital shaping filter comprising a shift register having a plurality of register stages serially connected to the output of said data encoder means, means for connecting said digital filter clock signal to each of said shift register stages, first resistor ladder network means for forcing the time response of the register stages to the input to the filter to be the Inverse Fourier transform of a substantially ideal low pass filter, and a second resistor ladder means for forcing the time response of the register stages to the input to the filter to be the Inverse Hilbert transform of a substantially ideal low pass filter, and the said sine-cosine generator comprising a plurality of serially connected shift register stages, means for connecting the carrier clock signal to each said register stage, first resistor ladder means connected to said register stages for producing a cosine wave output and second resistor ladder means connected to said registers for producing a sine wave output, the number of shift register stages being equal to one half the ratio of the carrier clock frequency to the carrier frequency and the values of the resistors for said first ladder network being determined by the formula Rki 1/(Xi 1 - X) for i 1 to M wherein X1, X2, X3...X2m are equi-spaced sample values of the outputs of the shift register stages and R1, R2, R3...Rm the values of the resistors connected to the first through mth shift register stage.