US3824562A
Expired / Lapsed
US
⏱️ 0.0 years remaining
High speed random access memory shift register
Assignee: United States Department of the Navy
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Filing: 1973-03-30
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Granted: 1974-07-16
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Expires: 1993-03-30
Abstract
Abstract A number of Random Access Memory (RAM) units are controlled by read-write logic, memory address counters, and a clock distribution function to provide a high speed shift register. The high speed capability is obtained through the use of a plurality of lower speed RAMs by sequentially processing input data from the first RAM to the second, then the third, etc. The output is taken from each RAM and fed to a latch so that while one RAM is providing data as an output, a subsequent RAM is able to manipulate and operate on subsequent data. Extremely long, high speed shift registers may be realized by this invention with particular interest in the area of signal processing of radar video returns.
Inventors
- 👤 L Leibowitz
- 👤 C Bates
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 22:58
CPC Classifications
G; G06; G06F; G06F5/00; G06F5/06; G06F5/10
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
155 words
A shift register for shifting data which is coordinated by a common clocking function comprising: input means for accepting data; clock distribution means for providing a pulse distribution sequence on a plurality of output lines; memory data register means coupled to said input means and to said plurality of output lines for gating the data in accordance with said pulse distribution sequence; random access memory means coupled to said memory data register means for reading, storing, and writing the gated data into and out of a particular memory location; memory control means coupled to said plurality of output lines and to said random access memory means for selecting said particular memory location; a first combining means coupled to said memory control means for writing data into a latch means; and a second combining means coupled to said memory control means and to said latch means for serially shifting the data out of said latch means.
Claim 2
Dependent Claim
155 words
A shift register for shifting data which is coordinated by a common clocking function comprising: input means for accepting data; clock distribution means for providing a pulse distribution sequence on a plurality of output lines; memory data register means coupled to said input means and to said plurality of output lines for gating the data in accordance with said pulse distribution sequence; random access memory means coupled to said memory data register means for reading, storing, and writing the gated data into and out of a particular memory location; memory control means coupled to said plurality of output lines and to said random access memory means for selecting said particular memory location; a first combining means coupled to said memory control means for writing data into a latch means; and a second combining means coupled to said memory control means and to said latch means for serially shifting the data out of said latch means.
Claim 3
Dependent Claim
21 words
The shift register as claimed in claim 1 wherein said memory control means include addressing control circuit and read-write control logic.
Claim 4
Dependent Claim
53 words
The shift register as claimed in claim 1 wherein the clock distribution means has N output lines and a first pulse of said pulse distribution sequence is provided on a first output line, the second pulse is provided on the second output line and the Nth pulse is provided on output line N.
Claim 5
Dependent Claim
23 words
The shift register as claimed in claim 3 wherein said clock distribution means further includes means for cyclically repeating said pulse distribution sequence.
References Cited (Backward Citations)
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-07-15 | 1978-01-14 | 1978-07-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-07-15 | 1982-01-14 | 1982-07-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-07-15 | 1986-01-14 | 1986-07-16 | $7700.00 | Window Closed / Lapsed |