US3735361A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Information store system having data block shift registers
Assignee: Individual
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Filing: 1971-08-30
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Granted: 1973-05-22
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Expires: 1991-08-30
Abstract
Abstract In an information processing system operating under the control of programmes of instruction-words on data blocks each of which is an orderly assembly of bits, an optimized average access store system comprises a plurality of block shift registers, each addressable as a memory section and each having a number of shift block positions at least equal to the total number of information block lines which may be stored in the memory section, and a selection device which upon reception of an address of a section and of an address of a block in said section controls a shift of the block lines in said section up to the coincidence of the addressed block with a read/write station associated with the addressed memory section. The selection device includes an addressing table which may or not be an associative address store or a random-access store and means for determining the optimal direction to impart to said controlled shift when the shift register constituting said section is shiftable in both directions. At least one index block may be provided in a block shift register, when desired, for easing and/or speeding the selection operations.
Inventors
- 👤 J Tasso
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 09:06
CPC Classifications
G; G11; G11C; G11C19/00
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
336 words
For a programme-controlled information processing system operating on multi-bit data blocks, a large capacity random access like store, comprising: a plurAlity of addressable memory sections each having simultaneously controllable shift registers equal in number to the number of bits in a data block to constitute a data block shift register of addressable block line positions and being individually controllable for a step-by-step operation in both directions; a memory request address code register, each address code therein comprising a memory section address code and a data block position address code; a table for memorizing data block position address codes up to at most one data block position address code per memory section; first and second data block position address code registers; means responsive to the introduction of a fresh memory request address code into said memory request address code register for transferring the data block position address code of said memory request to said first data block position address code register, transferring the data block position address code of the location of the table corresponding to the addressed memory section of said fresh request to the said second data block position address code register and substituting at said location of the table the fresh data block position address code for the former one; means detecting the sign of the difference between the codes in said first and second data block position address code registers; means responsive to the output of said sign detecting means for conditioning an activation of a step-by-step rotation of the addressed memory section in the direction defined by said sign and for simultaneously controlling a step-by-step modification of the content of said second data block address position register in a direction defined by said sign; and means permanently comparing the contents of said first and second registers during said modification of content of said second register up to code equality and stopping the activation of the rotation in the addresses memory section and the modification of said content when such equality is detected.
Claim 2
Dependent Claim
336 words
For a programme-controlled information processing system operating on multi-bit data blocks, a large capacity random access like store, comprising: a plurAlity of addressable memory sections each having simultaneously controllable shift registers equal in number to the number of bits in a data block to constitute a data block shift register of addressable block line positions and being individually controllable for a step-by-step operation in both directions; a memory request address code register, each address code therein comprising a memory section address code and a data block position address code; a table for memorizing data block position address codes up to at most one data block position address code per memory section; first and second data block position address code registers; means responsive to the introduction of a fresh memory request address code into said memory request address code register for transferring the data block position address code of said memory request to said first data block position address code register, transferring the data block position address code of the location of the table corresponding to the addressed memory section of said fresh request to the said second data block position address code register and substituting at said location of the table the fresh data block position address code for the former one; means detecting the sign of the difference between the codes in said first and second data block position address code registers; means responsive to the output of said sign detecting means for conditioning an activation of a step-by-step rotation of the addressed memory section in the direction defined by said sign and for simultaneously controlling a step-by-step modification of the content of said second data block address position register in a direction defined by said sign; and means permanently comparing the contents of said first and second registers during said modification of content of said second register up to code equality and stopping the activation of the rotation in the addresses memory section and the modification of said content when such equality is detected.
Claim 3
Dependent Claim
85 words
A store according to claim 1, wherein at least one read-write station is associated with each memory section and wherein at least one index block is provided intervening between data blocks, recording a distinctive configuration code with respect to any data block configuration code, in each of the said memory sections, comprising the further combination of: means detecting the position at said read-write station of the said index block and temporarily stopping the modification of the content of said second register at each such detection.
Claim 4
Dependent Claim
44 words
A store according to claim 1, wherein said table comprises as many data block position address code locations as there are memory sections and said table is addressable from a decoder of the memory section address code in said memory request address code register.
Claim 5
Dependent Claim
44 words
A store according to claim 1, wherein said table comprises as many data block position address code locations as there are memory sections and said table is associately addressable from the memory section address codes in said memory request address codes from said register.
Claim 6
Dependent Claim
163 words
A store according to claim 1, wherein said table comprises a restricted number of code locations with respect to the number of memory sections and is of the associative search type including a rejection arrangement of part of its content for accomodation of fresh content therein, comprising the further combination of: means for detecting the position address of a data block on which an addressed memory is stopped; comparator means comparing the memory section address code in a fresh memory request address code with the memory section address codes of the content of said table; means responsive to a positive answer of said comparator means for enabling the said means transferring into the second data block position address code register the data block position address code from the memory section addressed location of said table; and means responsive to a negativE answer from said comparator means for introduction of the position address code from said detecting means into the second of said registers.
Claim 7
Dependent Claim
65 words
A store according to claim 5, further comprising: means defining a predetermined position address code of a data block in the said memory sections; and means activated on a rejection operation of the said table, introducing the said predetermined position address code into the first of said registers and the data block position address code of the rejected information into the second of said registers.
Claim 8
Dependent Claim
69 words
A store according to claim 1, wherein the said shift registers are of the volatile bit storing type, said system further comprising: means controlling a permanent to-and-fro shift of a small amplitude in any unaddressed memory section; and means responsive to a memory section request in said memory request address code register for inhibiting the application of the output of said to-and-fro controlling means to the said addressed section.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-05-21 | 1976-11-20 | 1977-05-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-05-21 | 1980-11-20 | 1981-05-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-05-21 | 1984-11-20 | 1985-05-22 | $7700.00 | Window Closed / Lapsed |