Arbiter circuits

Claim 2

An infinite-resolution arbiter circuit comprising: a first and second finite resolution arbiter circuit each having at least two inputs and corresponding outputs, each said finite resolution arbiter circuit providing signals on each output when signals are applied within the time resolution capability of the arbiter, each said finite resolution arbiter circuit providing a signal on only the output corresponding to the input to which a signal is applied at a time earlier than the resolution time of the finite resolution arbiter with respect to a signal applied to the other input of the finite resolution arbiter, one input of the second finite resolution arbiter being connected to one output of the first finite resolution arbiter by a time delay element, the other input of the second arbiter being connected directly to the other output of the first finite resolution arbiter, the time delay of the delay element being greater than the sum of the resolution times of the first and second finite resolution arbiters, whereby only one signal is obtained within known time at an output of the second finite resolution arbiter regardless of how close in time signals are applied to the inputs of the first finite resolution arbiter with very, very low possibility that the other signal might also be obtained on the other output of the second finite resolution arbiter.

Claim 3

A finite-resolution arbiter circuits comprising a first and second C'' circuit, the output of each C'' circuit being connected to the blocking input of the other C'' circuit, the transmit inputs of the C'' circuits constituting the inputs of the arbiter circuit, and the output terminals of the C'' circuits constituting the corresponding outputs of the arbiter circuit, each said C'' circuit comprising, a set-reset flip-flop circuit, said flip-flop circuit comprising a first and second NAND gate each having two inputs and one output, the output of each gate being connected to one input of the other gate to form the flip flop circuit, the unconnected input of one NAND gate being designated a ''''set'''' input of the flip flop, the unconnected input of the other NAND gate being designated as the ''''reset'''' input, the output of the NAND gate to which the reset input is connected being designated as the output of the flip flop, a threshold element connected to said flip flop output and to the output of the C'' circuit, said threshold element being a NOT gate, the threshold being adjusted to be between the metastable state level and the level of the output in the ''''set'''' condition, the reset input of the flip flop being the transmit input of the C'' circuit and the set input of the flip flop being the blocking input of the C'' circuit.

Claim 4

A finite-resolution arbiter circuits comprising a first and second C'' circuit, the output of each C'' circuit being connected to the blocking input of the other C'' circuit, the transmit inputs of the C'' circuits constituting the inputs of the arbiter circuit, and the output terminals of the C'' circuits constituting the corresponding outputs of the arbiter circuit, each said C'' circuit comprising, a set-reset flip-flop circuit, said flip-flop circuit comprising a first and second NAND gate each having two inputs and one output, the output of each gate being connected to one input of the other gate to form the flip flop circuit, the unconnected input of one NAND gate being designated a ''''set'''' input of the flip flop, the unconnected input of the other NAND gate being designated as the ''''reset'''' input, the output of the NAND gate to which the reset input is connected being designated as the output of the flip flop, a threshold element connected to said flip flop output and to the output of the C'' circuit, said threshold element being a NOT gate, the threshold being adjusted to be between the metastable state level and the level of the output in the ''''set'''' condition, the reset input of the flip flop being the transmit input of the C'' circuit and the set input of the flip flop being the blocking input of the C'' circuit.

Claim 5

A finite-resolution arbiter circuit comprising, a first and second C'' circuit, each said C'' circuit comprising, a set-reset flip-flop circuit, said flip flop circuit comprising a first and second NAND gate each having two inputs and one output, the output of each gate being connected to one input of the other gate to form the flip-flop circuit, the unconnected input of one NAND gate being designated a ''''set'''' input of the flip flop, the unconnected input of the other NAND gate being designated as the ''''reset'''' input, the output of the NAND gate to which the reset input is connected being designated as the output of the flip flop, a threshold element connected to said flip flop output and to the output of the C'' circuit, said threshold element being a NOT gate, the threshold being adjusted to be between the metastable state level of the flip flop and the level of the output of the flip flop in the ''''set'''' condition, the reset input of the flip-flop being the transmit input of the C'' circuit and the set input of the flip flop being the blocking input of the C'' circuit, a first and second delay element, said first delay element being connected between the transmit input of the first C'' circuit and the blocking input of the second C'' circuit, said second delay element being connected between the transmit input of the second C'' circuit and the blocking input of the first C'' circuit, the transmit inputs of the C'' circuits constituting the inputs of the arbiter circuit, and the output terminal of the C'' circuits constituting the corresponding output of the arbiter circuit.

Claim 6

A finite-resolution arbiter circuit comprising, a first and second C'' circuit, each said C'' circuit comprising, a set-reset flip-flop circuit, said flip flop circuit comprising a first and second NAND gate each having two inputs and one output, the output of each gate being connected to one input of the other gate to form the flip-flop circuit, the unconnected input of one NAND gate being designated a ''''set'''' input of the flip flop, the unconnected input of the other NAND gate being designated as the ''''reset'''' input, the output of the NAND gate to which the reset input is connected being designated as the output of the flip flop, a threshold element connected to said flip flop output and to the output of the C'' circuit, said threshold element being a NOT gate, the threshold being adjusted to be between the metastable state level of the flip flop and the level of the output of the flip flop in the ''''set'''' condition, the reset input of the flip-flop being the transmit input of the C'' circuit and the set input of the flip flop being the blocking input of the C'' circuit, a first and second delay element, said first delay element being connected between the transmit input of the first C'' circuit and the blocking input of the second C'' circuit, said second delay element being connected between the transmit input of the second C'' circuit and the blocking input of the first C'' circuit, the transmit inputs of the C'' circuits constituting the inputs of the arbiter circuit, and the output terminal of the C'' circuits constituting the corresponding output of the arbiter circuit.

Claim 7

A finite resolution arbiter circuit comprising, an OR circuit, a plurality of C'' circuits, each said C'' circuit comprising, a set-reset flip flop circuit, said flip flop circuit comprising a first and second NAND gate each having two inputs and one output, the outputs of each gate being connected to one input of the other gate to form the flip-flop circuit, the unconnected input of one NAND gate being designated a ''''set'''' input of the flip flop, the unconnected input of the other NAND gate being designated as the ''''reset'''' input, the output of the NAND gate to which the reset input is connected being designated as the output of the flip flop, a thReshold element connected to said flip flop output and to the output of the C'' circuit, said threshold element being a NOT gate, the threshold being adjusted to be between the meta-stable state level of the flip flop and the level of the output of the flip flop in the ''''set'''' condition, the reset input of the flip flop being the transmit input of the C'' circuit and the set input of the flip flop being the blocking input of the C'' circuit, the outputs of said C'' circuits being connected to the inputs of said OR circuit, the output of said OR circuit being connected to the blocking inputs of said C'' circuits, the transmit inputs of the C'' circuits constituting the inputs of the arbiter circuits, and the output terminals of the C'' circuits constituting the corresponding outputs of the arbiter circuit.

Claim 8

A finite resolution arbiter circuit comprising, an OR circuit, a plurality of C'' circuits, each said C'' circuit comprising, a set-reset flip flop circuit, said flip flop circuit comprising a first and second NAND gate each having two inputs and one output, the outputs of each gate being connected to one input of the other gate to form the flip-flop circuit, the unconnected input of one NAND gate being designated a ''''set'''' input of the flip flop, the unconnected input of the other NAND gate being designated as the ''''reset'''' input, the output of the NAND gate to which the reset input is connected being designated as the output of the flip flop, a thReshold element connected to said flip flop output and to the output of the C'' circuit, said threshold element being a NOT gate, the threshold being adjusted to be between the meta-stable state level of the flip flop and the level of the output of the flip flop in the ''''set'''' condition, the reset input of the flip flop being the transmit input of the C'' circuit and the set input of the flip flop being the blocking input of the C'' circuit, the outputs of said C'' circuits being connected to the inputs of said OR circuit, the output of said OR circuit being connected to the blocking inputs of said C'' circuits, the transmit inputs of the C'' circuits constituting the inputs of the arbiter circuits, and the output terminals of the C'' circuits constituting the corresponding outputs of the arbiter circuit.

Claim 9

A finite resolution arbiter circuit comprising: a NOR circuit, a plurality of C circuits, each said C circuit having at least two inputs and one output, the output of the C circuit being a zero when all inputs are zero, the output of the C circuit being a one when all inputs are one, the output of the C circuit being unchanged by a change in the inputs unless all inputs are either ones or zeros, the outputs of said C circuits being connected to the inputs of said NOR circuit, the output of said NOR circuit being connected to an input of each of the plurality of C circuits, the other inputs of the C circuits constituting the inputs of the arbiter circuit.

Claim 10

A finite resolution arbiter circuit comprising: a NOR circuit, a plurality of C circuits, each said C circuit having at least two inputs and one output, the output of the C circuit being a zero when all inputs are zero, the output of the C circuit being a one when all inputs are one, the output of the C circuit being unchanged by a change in the inputs unless all inputs are either ones or zeros, the outputs of said C circuits being connected to the inputs of said NOR circuit, the output of said NOR circuit being connected to an input of each of the plurality of C circuits, the other inputs of the C circuits constituting the inputs of the arbiter circuit.

Claim 11

An infinite resolution arbiter circuit comprising: a first and second arbiter circuit each having finite resolution and a plurality of inputs and the same number of outputs, one input of the second arbiter being directly connected to an output of the first arbiter, a second input of the second arbiter being connected to a different output of the first arbiter through a first time delay element whose time delay is greater than the sum of the resolution of the first and second arbiters, succeeding inputs of the second arbiter being connected to different outputs of the first arbiter through time delay elements which differ from each other and said first time delay by a time delay at least as great as the sum of the resolutions of the first and second arbiters, and means for initializing the inputs to the first arbiter in response to outputs of the second arbiter. said finite resolution arbiter circuit providing signals on each output when signals are applied within the time resolution capability of the arbiter, said arbiter circuit providing a signal on only the output corresponding to the input to which a signal is applied at a time earlier than the resolution of the arbiter with respect to signals applied to the other inputs of the arbiter.

Claim 12

An infinite resolution arbiter circuit comprising: a first and second arbiter circuit each having finite resolution and a plurality of inputs and the same number of outputs, one input of the second arbiter being directly connected to an output of the first arbiter, a second input of the second arbiter being connected to a different output of the first arbiter through a first time delay element whose time delay is greater than the sum of the resolution of the first and second arbiters, succeeding inputs of the second arbiter being connected to different outputs of the first arbiter through time delay elements which differ from each other and said first time delay by a time delay at least as great as the sum of the resolutions of the first and second arbiters, and means for initializing the inputs to the first arbiter in response to outputs of the second arbiter. said finite resolution arbiter circuit providing signals on each output when signals are applied within the time resolution capability of the arbiter, said arbiter circuit providing a signal on only the output corresponding to the input to which a signal is applied at a time earlier than the resolution of the arbiter with respect to signals applied to the other inputs of the arbiter.

Claim 13

An infinite resolution arbiter circuit comprising: a plurality of finite resolution arbiter stages, each having two inputs and two outputs, one input of any stage other than the first stage being directly connected to an output of the preceding stage, and the other input of any stage other than the first stage being connected to the other output of the preceding stage by a time delay element whose delay is greater than the sum of the resolution times of the connected stages, said finite resolution arbiter circuit providing signals on each output when signals are applied within the time resolution capability of the arbiter, said arbiter circuit providing a signal on only the output corresponding to the input to which a signal is applied at a time earlier than the resolution of the arbiter with respect to signals applied to the other inputs of the arbiter.

Claim 14

An infinite resolution arbiter circuit comprising: a plurality of finite resolution arbiter stages, each having two inputs and two outputs, one input of any stage other than the first stage being directly connected to an output of the preceding stage, and the other input of any stage other than the first stage being connected to the other output of the preceding stage by a time delay element whose delay is greater than the sum of the resolution times of the connected stages, said finite resolution arbiter circuit providing signals on each output when signals are applied within the time resolution capability of the arbiter, said arbiter circuit providing a signal on only the output corresponding to the input to which a signal is applied at a time earlier than the resolution of the arbiter with respect to signals applied to the other inputs of the arbiter.

Claim 15

A finite-resolution arbiter circuit comprising: a first and second C'' circuit, each said C'' circuit having a transmit input, a blocking input, and one output, and being so constructed and arranged that: said C'' circuit output is a one when the transmit input becomes a one before the blocking input becomes a one, said C'' circuit output is a zero when the blocking input becomes a one before the transmit input becomes a one, said CC'' circuit output becomes a zero when the transmit input is a zero regardless of whether the blocking input is a one or a zero, the output of each C'' circuit being connected to the blocking input of the other C'' circuit, the transmit inputs of the C'' circuits constituting the inputs of the arbiter circuit, and the output terminals of the C'' circuits constituting the corresponding outputs of the arbiter circuit.

Claim 16

A finite-resolution arbiter circuit comprising: a first and second C'' circuit, each said C'' circuit having a transmit input, a blocking input, and one output, and being so constructed and arranged that: said C'' circuit output is a one when the transmit input becomes a one before the blocking input becomes a one, said C'' circuit output is a zero when the blocking input becomes a one before the transmit input becomes a one, said CC'' circuit output becomes a zero when the transmit input is a zero regardless of whether the blocking input is a one or a zero, the output of each C'' circuit being connected to the blocking input of the other C'' circuit, the transmit inputs of the C'' circuits constituting the inputs of the arbiter circuit, and the output terminals of the C'' circuits constituting the corresponding outputs of the arbiter circuit.

Claim 17

A finite-resolution arbiter circuit comprising, a first and second C'' circuit, each said C'' circuit having a transmit input, a blocking input, and one output, and being so constructed and arranged that: said C'' circuit output is a one when the transmit input becomes a one before the blocking input becomes a one, said C'' circuit output is a zero when the blocking input becomes a one before the transmit input becomes a one, said C'' circuit output becomes a zero when the transmit input is a zero regardless of whether the blocking input is a one or a zero, first and second delay elements, said first delay element being connected between the transmit input of the first C'' circuit and the blocking input of the second C'' circuit, said second delay element being connected between the transmit input of the second C'' circuit and the blocking input of the first C'' circuit, the transmit inputs of the C'' circuits constituting the inputs of the arbiter circuit, and the output terminals of the C'' circuits constituting the corresponding outputs of the arbiter circuit.

Claim 18

A finite-resolution arbiter circuit comprising, a first and second C'' circuit, each said C'' circuit having a transmit input, a blocking input, and one output, and being so constructed and arranged that: said C'' circuit output is a one when the transmit input becomes a one before the blocking input becomes a one, said C'' circuit output is a zero when the blocking input becomes a one before the transmit input becomes a one, said C'' circuit output becomes a zero when the transmit input is a zero regardless of whether the blocking input is a one or a zero, first and second delay elements, said first delay element being connected between the transmit input of the first C'' circuit and the blocking input of the second C'' circuit, said second delay element being connected between the transmit input of the second C'' circuit and the blocking input of the first C'' circuit, the transmit inputs of the C'' circuits constituting the inputs of the arbiter circuit, and the output terminals of the C'' circuits constituting the corresponding outputs of the arbiter circuit.

Claim 19

A finite-resolution arbiter circuit comprising: an OR circuit, a plurality of C'' circuits, each said C'' circuit having a transmit input, a blocking input, and one output, and being so constructed and arranged that: said C'' circuit output is a one when the transmit input becomes a one before the blocking input becomes a one, said C'' circuit output is a zero when the blocking input becomes a one before the transmit input becomes a one, said C'' circuit output becomes a zero when the transmit input is a zero regardless of whether the blocking input is a one or a zero, the outputs of said C'' circuits being connected to the inputs of said OR circuit, the output of said OR circuit being connected to the blocking input of said C'' circuits, the transmit inputs of the C'' circuits constituting the inputs of the arbiter circuit, and the output terminals of the C'' circuits constituting the corresponding outputs of the arbiter circuit.

Claim 20

A finite-resolution arbiter circuit comprising: an OR circuit, a plurality of C'' circuits, each said C'' circuit having a transmit input, a blocking input, and one output, and being so constructed and arranged that: said C'' circuit output is a one when the transmit input becomes a one before the blocking input becomes a one, said C'' circuit output is a zero when the blocking input becomes a one before the transmit input becomes a one, said C'' circuit output becomes a zero when the transmit input is a zero regardless of whether the blocking input is a one or a zero, the outputs of said C'' circuits being connected to the inputs of said OR circuit, the output of said OR circuit being connected to the blocking input of said C'' circuits, the transmit inputs of the C'' circuits constituting the inputs of the arbiter circuit, and the output terminals of the C'' circuits constituting the corresponding outputs of the arbiter circuit.