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US3822385A Expired / Lapsed US ⏱️ 0.0 years remaining

Noise pulse rejection circuit

Assignee: Nortel Networks Technology Corp
•
Filing: 1973-09-14
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Granted: 1974-07-02
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Expires: 1993-09-14
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Abstract

Abstract A circuit for rejecting pulses having a width less than a predetermined amount uses a single amplifier. The pulses are fed to the amplifier through a resistance-capacitance charging circuit. The resistance element is shunted by a pair of switched low impedance circuits which are controlled by the output signal of the amplifier to selectively permit current flow through only one of the circuits.

Inventors

  • 👤 I Kayalioglu

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-25 10:27
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/01; H03K3/013; G; G01; G01R; G01R29/00; G01R29/02; G01R29/027; G01R29/0273; H03K3/02; H03K3/023; H03K3/0233; H03K3/02337

Claims Analysis

Total Claims: 9
Claim 1
Independent Claim 128 words
A pulse rejection circuit comprising: an input terminal for connection to a source of pulses; an operational amplifier having an output terminal, an inverting input, and a non-inverting input; a resistance element connected between the input terminal and said inverting input; a capacitance element having one end connected to said inverting input, and the other end connected to said non-inverting input and to an output port for connection to a source of reference potential; a pair of oppositely poled unidirectional current devices connected in parallel and across said resistance element; a pair of switch means, each one connected in series with a respective one of said devices, said switch means being responsive to the signal appearing on said output terminal for selectively permitting current flow through said devices.
Claim 2
Dependent Claim 128 words
A pulse rejection circuit comprising: an input terminal for connection to a source of pulses; an operational amplifier having an output terminal, an inverting input, and a non-inverting input; a resistance element connected between the input terminal and said inverting input; a capacitance element having one end connected to said inverting input, and the other end connected to said non-inverting input and to an output port for connection to a source of reference potential; a pair of oppositely poled unidirectional current devices connected in parallel and across said resistance element; a pair of switch means, each one connected in series with a respective one of said devices, said switch means being responsive to the signal appearing on said output terminal for selectively permitting current flow through said devices.
Claim 3
Dependent Claim 14 words
A circuit as defined in claim 1 wherein said unidirectional current devices are diodes.
Claim 4
Dependent Claim 14 words
A circuit as defined in claim 2 wherein said switch means are bipolar transistors.
Claim 5
Dependent Claim 127 words
A pulse rejection circuit comprising: an input terminal for connection to a source of pulses; an operational amplifier having an output terminal, an inverting input, and a non-inverting input; a resistance element connected between the input terminal and said inverting input; a capacitance element having one end connected to said inverting input, and the other end connected to said non-inverting input and to an output port for connection to a source of reference potential; a pair of opposite type bipolar transistors having their base electrodeS connected to said output terminal, their collector electrodes connected to said inverting input, and their emitter electrodes connected to said input terminal through a respective diode, said diodes being poled in the same direction as the emitter-base junction of their respective transistor.
Claim 6
Dependent Claim 127 words
A pulse rejection circuit comprising: an input terminal for connection to a source of pulses; an operational amplifier having an output terminal, an inverting input, and a non-inverting input; a resistance element connected between the input terminal and said inverting input; a capacitance element having one end connected to said inverting input, and the other end connected to said non-inverting input and to an output port for connection to a source of reference potential; a pair of opposite type bipolar transistors having their base electrodeS connected to said output terminal, their collector electrodes connected to said inverting input, and their emitter electrodes connected to said input terminal through a respective diode, said diodes being poled in the same direction as the emitter-base junction of their respective transistor.
Claim 7
Dependent Claim 21 words
A circuit as defined in claim 4, further comprising a third diode connected across a first portion of said resistance element.
Claim 8
Dependent Claim 29 words
A circuit as defined in claim 5 further comprising a fourth diode connected across a second portion of said resistance element, said third and fourth diodes being poled oppositely.
Claim 9
Dependent Claim 46 words
A circuit as defined in claim 4 wherein said resistance element is a potentiometer, and further comprising fifth and sixth diodes connected serially in opposition and across the ends of the potentiometer, the adjustable terminal of the potentiometer being connected to the junction of said diodes.

References Cited (Backward Citations)

US2666135A Cited
US3219838A Cited
US3132263A Cited
US3387221A Cited
US3693101A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1977-07-01 1977-12-31 1978-07-02 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1981-07-01 1981-12-31 1982-07-02 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1985-07-01 1985-12-31 1986-07-02 $7700.00 Window Closed / Lapsed

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